An alternative test method for the dual-port SRAM through the DesignWare SATA AHCI implementation in 3-D IC structures

The conventional methods for testing the Dual Port Random Access Memories (DPRAM) may not be suitable for the Three-Dimensional Integrated Circuit (3-D IC) structures, due to their limited test vectors with heterogeneous integration. This paper takes an Application Specific Integrated Chips (ASIC) approach to gain some insight into the Front-end behavioral testing and backend routability of the dual port memories with complex Serial Advanced Technology Attachment (Serial-ATA) design, in a 3-D IC structure. The presented implementation used commercially available Dual Port memories from the two different vendors. The commercially available DesignWare Advanced Host Controller Interface (SATA/AHCI), which is based on the SATA 2.6 AHCI host and external SATA (eSATA) standard bus architecture, with My_foundry’s 14nm low power process (14lp) technologies for the logical and physical implementations. The methodology evaluates the memory quality and performance/characteristics, in terms of timing, power and area. This paper shows memory testing in both implementation/verification in a readily built-up SATA test environment.

An Alternative Test Method for the Dual Port SRAM Memory through the Designware SATA AHCI Implementation in 3-D IC Structures

Background: It is being considered that conventional methods for testing the dual port memories might not be suitable for the Three-Dimensional Integrated Circuit (3-D IC) structures due to the presence of the limited test vectors with heterogeneous integration. Objective: Find out a novel test methodology DPRAMs in 3-D IC structures. Methods: This paper has taken the approach called as Application Specific Integrated Chips(ASIC) to gain insights on Front-End behavioral testing and Back-End routability of the dual port memories integrated with complex Serial Advanced Technology Attachment (Serial-ATA) design, in a 3-D IC structure. The presented implementation is using commercially available dual port memories from two different vendors. The commercially available DesignWare Advanced Host Controller Interface (SATA/AHCI) is based on the Serial Advanced Technology Attachment (SATA 2.6), AHCI host and external SATA (eSATA) standard bus architecture and being used with My_foundry’s 14nm Low Power (14LP) process technology for logical and physical implementations. Results: This paper shows memory testing in both implementation/verification in a readily built-up SATA test environment. Conclusion: It is being considered that the approach described here might be used as a tool/environment for evaluating any vendor's DPRAMs/2Ports RAMs/2Ports Register Files. As a result, it offers an alternative to the traditional test methodology.

High-Speed Transmission and Mass Data Storage Solutions for Large-Area and Arbitrarily Structured Fabrication through Maskless Lithography

This paper presents the implementation aspects and design of high-speed data transmission in laser direct-writing lithography. With a single field programmable gate array (FPGA) chip, mass data storage management, transmission, and synchronization of each part in real-time were implemented. To store a massive amount of data and transmit data with high bandwidth, a serial advanced technology attachment (SATA) intellectual property (IP) was developed on Xilinx Virtex-6 FPGA. In addition, control of laser beam power, collection of status read back data of the lithography laser through an analog-to-digital converter, and synchronization of the positioning signal were implemented on the same FPGA. A data structure for each unit with a unique exposure dose and other necessary information was established. Results showed that the maximum read bandwidth (240 MB/s) and maximum write bandwidth (200 MB/s) of a single solid-state drive conform to the data transmission requirement. The total amount of data meets the requirement of a large-area diffractive element approximately 102 cm2. The throughput has been greatly improved at meters per second or square centimeter per second. And test results showed that data transmission meets the requirement of the experiment.

A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

A low-jitter fractional spread-spectrum clock generator (SSCG) utilizing a fast-settling dual-charge-pump (CP) technique is developed for serial-advanced technology attachment (SATA) applications. The dual-CP architecture reduces a design area to 60% by shrinking an effective capacitance of a loop filter. Moreover, the settling-time is reduced by 4 μs to charge a current to the capacitor by only main-CP in initial period in settling-time. The SSCG is fabricated in a 0.13 μm CMOS and achieves settling time of 3.91 μs faster than 8.11 μs of a conventional SSCG. The random jitter and total jitter at 250 cycles at 1.5 GHz are less than 3.2 and 10.7 psrms, respectively. The triangular modulation signal frequency is 31.5 kHz and the modulation deviation is from −5000 ppm to 0 ppm at 1.5 GHz. The EMI reduction is 10.0 dB. The design area and power consumption are 300 × 700 μm and 18 mW, respectively.