Antarmuka Mikrokontroller IoT (ESP32) Dengan USB Host max3421e

Electronic equipment made using old technology or electronic equipment in the entry-level category has not been supported by networking equipment, so for the data communication process, the microcontroller requires interfacing facilities that are in accordance with the electronic equipment used, such as a USB port. With the microcontroller that supports IoT, it allows electronic equipment to communicate over the network. An IoT microcontroller such as the ESP32 is equipped with a WiFi feature but is not equipped with a USB controller feature, while the USB Host max3421e supports the communication process using SPI, so that those two microcontrollers can be used to form an interface using the SPI bus. This interface can be applied to electronic equipment with old technology and entry level electronic equipment for wireless communication. For the needs of making an interface between the ESP32 and max3421e, a software was developed by analyzing the SPI features of the ESP32 and the USB protocol according to the USB device state diagram. The results obtained are the handshake process between systems developed with USB devices in the Low-Speed ​​and Full-Speed ​​categories such as printers, flashdisk, bluetooth mouse and external hard disk, and the device descriptor data of each device tested can be read properly.

BEAM or MFA I inspired Nv Neurons using SPI and a MCU for line and line based polygon detection.

A companion publication to an opamp based Nv neuron architecture paper, this publication explores the use of inexpensive mouse optical sensors for shape recognition as polygons from line recognition networks, in sensor and two motor fusion in a TOMU/WOMU circuit using the SPI bus and a master -slave architecture. Lie Computability, is defined on discrete Tensor architectures, similar to computation on fields, in future work, field computing is proven to have the same complexity as integer lattices, though Lie Lattices embeddings in integer and complex lattices, proving MFA I and II architectures are equivalent in complexity, in both analog and digital worlds. Keywords: Tensor Flow, Tensor Architectures, Unsupervised Learning, Emergent A.I , procedural A.I, MFA I and II architectures, neuromodulation, SoC , TOMU/WOMU, SPI bus. What: We consider inexpensive 18 by 18 matrix 64 gray levels SPI interface, based photodetector components of optical mice. In this paper we consider the use of the SPI interface for the use of a master slave system of interface of an MCU to the optic processor for creating of BEAM circuitry using inexpensive MCU circuitry, such as the TOMU/WOMU. How: MFA I and MFA II architectures are fulfilled in both digital and analog circuitry, with a network architecture defined by a tensor notation, as described in a companion paper. Why: A digital fulfilment of a tensor architecture is defined and compared to Lego Mindstorm based deep learning and procedural algorithms for semantic segmentation and classification algorithms.

BEAM or MFA I inspired Nv Neurons using SPI and a MCU for line and line based polygon detection.

A companion publication to an opamp based Nv neuron architecture paper, this publication explores theuse of inexpensive mouse optical sensors for shape recognition as polygons from line recognitionnetworks, in sensor and two motor fusion in a TOMU/WOMU circuit using the SPI bus and a master-slave architecture. Lie Computability, is defined on discrete Tensor architectures, similar to computationon fields, in future work, field computing is proven to have the same complexity as integer lattices,though Lie Lattices embeddings in integer and complex lattices, proving MFA I and II architectures areequivalent in complexity, in both analog and digital worlds.Keywords: Tensor Flow, Tensor Architectures, Unsupervised Learning, Emergent A.I , procedural A.I,MFA I and II architectures, neuromodulation, MCU, SoC , TOMU/WOMU, SPI bus.What:We consider inexpensive 18 by 18 matrix 64 gray levels SPI interface, based photodetector componentsof optical mice. In this paper we consider the use of the SPI interface for the use of a master slave systemof interface of an MCU to the optic processor for creating of BEAM circuitry using inexpensive MCUcircuitry, such as the TOMU/WOMU.How:MFA I and MFA II architectures are fulfilled in both digital and analog circuitry, with a networkarchitecture defined by a tensor notation, as described in a companion paper.Why:A digital fulfilment of a tensor architecture is defined and compared to Lego Mindstorm based deeplearning and procedural algorithms for semantic segmentation and classification algorithms.

Design of a Low Cost Switching Board Enabling a Reconfigurable Remote Experiment

<p class="0abstract">Most of currently remote laboratories implementations include interactive experimentation. In this case, students use real devices and equipment to perform real experiments, which need some flexibility of interaction with the hardware platform. The hardware platform is composed of a Raspberry Pi as a lab server, a switching board (SB), a practical work circuit board and some measurement instruments. The SB is used to make configuration of experimentation by establishing connection between the practical work circuit and measurement instruments. During the experimentation process, students change the setup using a web page. In the background, the hardware configuration is realized using SB, which is controlled by the lab server. The purpose of this work is to develop a new SB in order to provide more possibilities, interaction flexibility with the hardware platform, ease of use, improve performance in response time and finally reduce the cost of the hardware. The SB is based on switches instead of relays. This board can be plugged directly on a Raspberry Pi to facilitate the assembly. It extends the “SPI” bus in order to control some electronic components such as digital potentiometers. Its use is illustrated with a circuit with multiple combinations.</p>