Spiking Neural Network-Based Near-Sensor Computing for Damage Detection in Structural Health Monitoring

In this work, we present an innovative approach for damage detection of infrastructures on-edge devices, exploiting a brain-inspired algorithm. The proposed solution exploits recurrent spiking neural networks (LSNNs), which are emerging for their theoretical energy efficiency and compactness, to recognise damage conditions by processing data from low-cost accelerometers (MEMS) directly on the sensor node. We focus on designing an efficient coding of MEMS data to optimise SNN execution on a low-power microcontroller. We characterised and profiled LSNN performance and energy consumption on a hardware prototype sensor node equipped with an STM32 embedded microcontroller and a digital MEMS accelerometer. We used a hardware-in-the-loop environment with virtual sensors generating data on an SPI interface connected to the physical microcontroller to evaluate the system with a data stream from a real viaduct. We exploited this environment also to study the impact of different on-sensor encoding techniques, mimicking a bio-inspired sensor able to generate events instead of accelerations. Obtained results show that the proposed optimised embedded LSNN (eLSNN), when using a spike-based input encoding technique, achieves 54% lower execution time with respect to a naive LSNN algorithm implementation present in the state-of-the-art. The optimised eLSNN requires around 47 kCycles, which is comparable with the data transfer cost from the SPI interface. However, the spike-based encoding technique requires considerably larger input vectors to get the same classification accuracy, resulting in a longer pre-processing and sensor access time. Overall the event-based encoding techniques leads to a longer execution time (1.49×) but similar energy consumption. Moving this coding on the sensor can remove this limitation leading to an overall more energy-efficient monitoring system.

BEAM or MFA I inspired Nv Neurons using SPI and a MCU for line and line based polygon detection.

A companion publication to an opamp based Nv neuron architecture paper, this publication explores the use of inexpensive mouse optical sensors for shape recognition as polygons from line recognition networks, in sensor and two motor fusion in a TOMU/WOMU circuit using the SPI bus and a master -slave architecture. Lie Computability, is defined on discrete Tensor architectures, similar to computation on fields, in future work, field computing is proven to have the same complexity as integer lattices, though Lie Lattices embeddings in integer and complex lattices, proving MFA I and II architectures are equivalent in complexity, in both analog and digital worlds. Keywords: Tensor Flow, Tensor Architectures, Unsupervised Learning, Emergent A.I , procedural A.I, MFA I and II architectures, neuromodulation, SoC , TOMU/WOMU, SPI bus. What: We consider inexpensive 18 by 18 matrix 64 gray levels SPI interface, based photodetector components of optical mice. In this paper we consider the use of the SPI interface for the use of a master slave system of interface of an MCU to the optic processor for creating of BEAM circuitry using inexpensive MCU circuitry, such as the TOMU/WOMU. How: MFA I and MFA II architectures are fulfilled in both digital and analog circuitry, with a network architecture defined by a tensor notation, as described in a companion paper. Why: A digital fulfilment of a tensor architecture is defined and compared to Lego Mindstorm based deep learning and procedural algorithms for semantic segmentation and classification algorithms.

BEAM or MFA I inspired Nv Neurons using SPI and a MCU for line and line based polygon detection.

A companion publication to an opamp based Nv neuron architecture paper, this publication explores theuse of inexpensive mouse optical sensors for shape recognition as polygons from line recognitionnetworks, in sensor and two motor fusion in a TOMU/WOMU circuit using the SPI bus and a master-slave architecture. Lie Computability, is defined on discrete Tensor architectures, similar to computationon fields, in future work, field computing is proven to have the same complexity as integer lattices,though Lie Lattices embeddings in integer and complex lattices, proving MFA I and II architectures areequivalent in complexity, in both analog and digital worlds.Keywords: Tensor Flow, Tensor Architectures, Unsupervised Learning, Emergent A.I , procedural A.I,MFA I and II architectures, neuromodulation, MCU, SoC , TOMU/WOMU, SPI bus.What:We consider inexpensive 18 by 18 matrix 64 gray levels SPI interface, based photodetector componentsof optical mice. In this paper we consider the use of the SPI interface for the use of a master slave systemof interface of an MCU to the optic processor for creating of BEAM circuitry using inexpensive MCUcircuitry, such as the TOMU/WOMU.How:MFA I and MFA II architectures are fulfilled in both digital and analog circuitry, with a networkarchitecture defined by a tensor notation, as described in a companion paper.Why:A digital fulfilment of a tensor architecture is defined and compared to Lego Mindstorm based deeplearning and procedural algorithms for semantic segmentation and classification algorithms.

Design & Verification of Serial Peripheral Interface (SPI) Protocol

SPI (Serial Peripheral Interface), which was introduced by the company Motorola, and it is a protocol for communication of serial synchronous about the communication among the master and slave device, which is also used to provide communiqué between microcontroller and many devices which are additional and similar to external Analog to the Digital Converters, Digital to Analog Converters, and EEPROMs. Now a days, communication protocols are at low end. There are two different Protocols: 1) Inter-I2C and 2) SPI. Both of these protocols are well designed for the communications between the Integrated Circuits for communication with On-Board Peripherals. SPI is most commonly used protocol for both intra-chip and inter-chip, and is used at low or medium speed of data-stream transfer. This paper introduces about the quality of SPI Interface Protocol with Single Master and Single Slave configuration, which involves 8-bit of the data transfer and all necessary incorporates features that required for modern applications such as ASIC or SOC (System on Chip). The SPI design is verified and implemented by using System Verilog to show their coverage code and their functional correctness, the entire RTL was written using Verilog for Synthesis and then the Verification architecture is written using System Verilog. The implementation is done using Spartan 3E.

Device for Current Test Pulse Development Through a Diode in a Direct Direction

The article is devoted to the development of a device that allows to generate control current pulses to determine the current-voltage characteristic of diodes in the forward direction. To implement the device, we use NI Digital Electronics FPGA Board, which includes FPGA XC3S500E Xilinx Spartan-3E FPGA and the Linear Technology LTC2624 chip, containing four 12-bit DACs. We consider the creation of a software module via VHDL language that generates 12-bit digital code to create rectangular voltage control pulses with a successively increasing amplitude and transmitted via SPI interface as the part of 32-bit data transfer protocol, using Xilinx WebPACK ISE software.