High Breakdown Voltage and Low Buffer Trapping in Superlattice GaN-on-Silicon Heterostructures for High Voltage Applications

The aim of this work is to demonstrate high breakdown voltage and low buffer trapping in superlattice GaN-on-Silicon heterostructures for high voltage applications. To this aim, we compared two structures, one based on a step-graded (SG) buffer (reference structure), and another based on a superlattice (SL). In particular, we show that: (i) the use of an SL allows us to push the vertical breakdown voltage above 1500 V on a 5 µm stack, with a simultaneous decrease in vertical leakage current, as compared to the reference GaN-based epi-structure using a thicker buffer thickness. This is ascribed to the better strain relaxation, as confirmed by X-Ray Diffraction data, and to a lower clustering of dislocations, as confirmed by Defect Selective Etching and Cathodoluminescence mappings. (ii) SL-based samples have significantly lower buffer trapping, as confirmed by substrate ramp measurements. (iii) Backgating transient analysis indicated that traps are located below the two-dimensional electron gas, and are related to CN defects. (iv) The signature of these traps is significantly reduced on devices with SL. This can be explained by the lower vertical leakage (filling of acceptors via electron injection) or by the slightly lower incorporation of C in the SL buffer, due to the slower growth process. SL-based buffers therefore represent a viable solution for the fabrication of high voltage GaN transistors on silicon substrate, and for the simultaneous reduction of trapping processes.

Transferless Inverted Graphene/Silicon Heterostructures Prepared by Plasma-Enhanced Chemical Vapor Deposition of Amorphous Silicon on CVD Graphene

The heterostructures of two-dimensional (2D) and three-dimensional (3D) materials represent one of the focal points of current nanotechnology research and development. From an application perspective, the possibility of a direct integration of active 2D layers with exceptional optoelectronic and mechanical properties into the existing semiconductor manufacturing processes is extremely appealing. However, for this purpose, 2D materials should ideally be grown directly on 3D substrates to avoid the transferring step, which induces damage and contamination of the 2D layer. Alternatively, when such an approach is difficult—as is the case of graphene on noncatalytic substrates such as Si—inverted structures can be created, where the 3D material is deposited onto the 2D substrate. In the present work, we investigated the possibility of using plasma-enhanced chemical vapor deposition (PECVD) to deposit amorphous hydrogenated Si (a-Si:H) onto graphene resting on a catalytic copper foil. The resulting stacks created at different Si deposition temperatures were investigated by the combination of Raman spectroscopy (to quantify the damage and to estimate the change in resistivity of graphene), temperature-dependent dark conductivity, and constant photocurrent measurements (to monitor the changes in the electronic properties of a-Si:H). The results indicate that the optimum is 100 °C deposition temperature, where the graphene still retains most of its properties and the a-Si:H layer presents high-quality, device-ready characteristics.

Design and optimization of tunneling photodetectors based on graphene/Al2O3/silicon heterostructures

Recent discoveries in the field of graphene-based heterostructures have led to the demonstration of high-performance photodetectors. However, the studies to date have been largely limited to the heterojunction with a Schottky barrier, restricted by an inevitable compromise between photoresponsivity and photodetectivity. Here, a new class of graphene-based tunneling photodetectors is introduced by inserting the Al2O3 tunneling layer between silicon and graphene. The photocarriers can tunnel through the designed insulator layer which simultaneously blocks the dark current, thus maintaining high photodetectivity with desirable photoresponsivity. We further modulate the thickness of the Al2O3 layer to explore the tunneling mechanism for the photocarriers, in which a photoresponsivity of 0.75 A/W, a high current ratio of 4.8 × 103 and a photodetectivity of 3.1 × 1012 Jones are obtained at a 13.3-nm-thick Al2O3 layer. In addition, the fabrication process is compatible with conventional semiconductor processing, providing further flexibility to large-scale integrated photodetectors with high performance.