Improved Pulse-Controlled Conductance Adjustment in Trilayer Resistors by Suppressing Current Overshoot

In this work, we demonstrate the enhanced synaptic behaviors in trilayer dielectrics (HfO2/Si3N4/SiO2) on highly doped n-type silicon substrate. First, the three dielectric layers were subjected to material and chemical analyses and thoroughly investigated via transmission electron microscopy and X-ray photoelectron spectroscopy. The resistive switching and synaptic behaviors were improved by inserting a Si3N4 layer between the HfO2 and SiO2 layers. The electric field within SiO2 was mitigated, thus reducing the current overshoot in the trilayer device. The reset current was considerably reduced in the trilayer device compared to the bilayer device without a Si3N4 layer. Moreover, the nonlinear characteristics in the low-resistance state are helpful for implementing high-density memory. The higher array size in the trilayer device was verified by cross-point array simulation. Finally, the multiple conductance adjustment was demonstrated in the trilayer device by controlling the gradual set and reset switching behavior.

Efficiency Enhanced Grating Coupler for Perfectly Vertical Fiber-to-Chip Coupling

In this work, a bidirectional grating coupler for perfectly vertical coupling is proposed. The coupling efficiency is enhanced using a silicon nitride (Si3N4) layer above a uniform grating. In the presence of Si3N4 layer, the back-reflected optical power into the fiber is diminished and coupling into the waveguide is increased. Genetic algorithm (GA) is used to optimize the grating and Si3N4 layer simultaneously. The optimal design obtained from GA shows that the average in-plane coupling efficiency is enhanced from about 57.5% (−2.5 dB) to 68.5% (−1.65 dB), meanwhile the average back-reflection in the C band is reduced from 17.6% (−7.5 dB) to 7.4% (−11.3 dB). With the help of a backside metal mirror, the average coupling efficiency and peak coupling efficiency are further increased to 87% (−0.6 dB) and 89.4% (−0.49 dB). The minimum feature size of the designed device is 266 nm, which makes our design easy to fabricate through 193 nm deep-UV lithography and lowers the fabrication cost. In addition, the coupler proposed here shows a wide-band character with a 1-dB bandwidth of 64 nm and 3-dB bandwidth of 96 nm. Such a grating coupler design can provide an efficient and cost-effective solution for vertical fiber-to-chip optical coupling of a Wavelength Division Multiplexing (WDM) application.

Studies on a Novel Qualification Method of Silicon Nitride Layer

In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.