design obfuscation Latest Research Papers

A Tutorial on Design Obfuscation: from Transistors to Systems

10.1109/lats53581.2021.9651741 ◽

2021 ◽

Author(s):

Samuel Pagliarini

Keyword(s):

Design Obfuscation

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ObfusGEM: Enhancing Processor Design Obfuscation Through Security-Aware On-Chip Memory and Data Path Design

The International Symposium on Memory Systems ◽

10.1145/3422575.3422798 ◽

2020 ◽

Author(s):

Michael Zuzak ◽

Ankur Srivastava

Keyword(s):

Data Path ◽

Processor Design ◽

Path Design ◽

On Chip ◽

Design Obfuscation

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On Leveraging Multi-threshold FinFETs for Design Obfuscation

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi49217.2020.00029 ◽

2020 ◽

Author(s):

Vinay C Patil ◽

Sandip Kundu

Keyword(s):

Design Obfuscation

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Design Obfuscation versus Test

2020 IEEE European Test Symposium (ETS) ◽

10.1109/ets48528.2020.9131590 ◽

2020 ◽

Author(s):

Farimah Farahmandi ◽

Ozgur Sinanoglu ◽

Ronald Blanton ◽

Samuel Pagliarini

Keyword(s):

Versus Test ◽

Design Obfuscation

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Memory Locking: An Automated Approach to Processor Design Obfuscation

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi.2019.00103 ◽

2019 ◽

Cited By ~ 1

Author(s):

Michael Zuzak ◽

Ankur Srivastava

Keyword(s):

Processor Design ◽

Design Obfuscation

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Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.23919/date.2019.8714856 ◽

2019 ◽

Cited By ~ 3

Author(s):

Mustafa M. Shihab ◽

Jingxiang Tian ◽

Gaurav Rajavendra Reddy ◽

Bo Hu ◽

William Swartz ◽

...

Keyword(s):

Design Obfuscation

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Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2017.2697960 ◽

2018 ◽

Vol 37 (2) ◽

pp. 273-285 ◽

Cited By ~ 14

Author(s):

Jaya Dofe ◽

Qiaoyan Yu

Keyword(s):

Dynamic State ◽

Level Design ◽

Design Obfuscation

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Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques

IEEE Transactions on Information Forensics and Security ◽

10.1109/tifs.2016.2601067 ◽

2017 ◽

Vol 12 (1) ◽

pp. 64-77 ◽

Cited By ~ 36

Author(s):

Arunkumar Vijayakumar ◽

Vinay C. Patil ◽

Daniel E. Holcomb ◽

Christof Paar ◽

Sandip Kundu

Keyword(s):

Physical Design ◽

Comprehensive Investigation ◽

Logic Level ◽

Design Obfuscation

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Security Against Hardware Trojan Attacks Through a Novel Chaos FSM and Delay Chains Array PUF Based Design Obfuscation Scheme

Cloud Computing and Security - Lecture Notes in Computer Science ◽

10.1007/978-3-319-27051-7_2 ◽

2015 ◽

pp. 14-24 ◽

Cited By ~ 3

Author(s):

Mingfu Xue ◽

Jian Wang ◽

Youdong Wang ◽

Aiqun Hu

Keyword(s):

Hardware Trojan ◽

Design Obfuscation

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Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014 ◽

10.7873/date2014.256 ◽

2014 ◽

Cited By ~ 9

Author(s):

Bao Liu ◽

Brandon Wang

Keyword(s):

Supply Chain ◽

Reconfigurable Logic ◽

Asic Design ◽

Design Obfuscation

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design obfuscation
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

A Tutorial on Design Obfuscation: from Transistors to Systems

ObfusGEM: Enhancing Processor Design Obfuscation Through Security-Aware On-Chip Memory and Data Path Design

On Leveraging Multi-threshold FinFETs for Design Obfuscation

Design Obfuscation versus Test

Memory Locking: An Automated Approach to Processor Design Obfuscation

Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming

Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques

Security Against Hardware Trojan Attacks Through a Novel Chaos FSM and Delay Chains Array PUF Based Design Obfuscation Scheme

Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks

Export Citation Format

design obfuscationRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

A Tutorial on Design Obfuscation: from Transistors to Systems

ObfusGEM: Enhancing Processor Design Obfuscation Through Security-Aware On-Chip Memory and Data Path Design

On Leveraging Multi-threshold FinFETs for Design Obfuscation

Design Obfuscation versus Test

Memory Locking: An Automated Approach to Processor Design Obfuscation

Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming

Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques

Security Against Hardware Trojan Attacks Through a Novel Chaos FSM and Delay Chains Array PUF Based Design Obfuscation Scheme

Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks

design obfuscation
Recently Published Documents