Transparent Control Flow Transfer between CPU and Accelerators for HPC

Heterogeneous platforms with FPGAs have started to be employed in the High-Performance Computing (HPC) field to improve performance and overall efficiency. These platforms allow the use of specialized hardware to accelerate software applications, but require the software to be adapted in what can be a prolonged and complex process. The main goal of this work is to describe and evaluate mechanisms that can transparently transfer the control flow between CPU and FPGA within the scope of HPC. Combining such a mechanism with transparent software profiling and accelerator configuration could lead to an automatic way of accelerating regular applications. In this work, a mechanism based on the ptrace system call is proposed, and its performance on the Intel Xeon+FPGA platform is evaluated. The feasibility of the proposed approach is demonstrated by a working prototype that performs the transparent control flow transfer of any function call to a matching hardware accelerator. This approach is more general than shared library interposition at the cost of a small time overhead in each accelerator use (about 1.3 ms in the prototype implementation).

Computational Load Analysis of a Galileo OSNMA-Ready Receiver for ARM-Based Embedded Platforms

Many GNSS applications have been experiencing some constantly growing needs in terms of security and reliability. To address some of them, both GPS and Galileo are proposing evolutions of their legacy civil signals, embedding features of authentication. This paper focuses on the Galileo Open Signal Navigation Message Authentication (OSNMA) and describes its implementation within a real-time software receiver for ARM-based embedded platforms. The innovative contributions of the paper include the software profiling analysis for the OSNMA add on, along with the comparison among performances obtained with different platforms. In addition, specific evaluations on the computational load of the whole receiver complete the analysis. The receiver used for the implementation belongs to the NGene receivers family—real-time fully-software GPS and Galileo receivers, tailored for different platforms and sharing the same core processing. In detail, the paper deals with the introduction of the OSNMA support inside the eNGene, the version of the receiver executable by ARM-based embedded platforms.