scholarly journals High Performance Error Detection with Different Set Cyclic Codes for Memory Applications

2013 ◽  
Vol 8 (4) ◽  
pp. 07-12
Author(s):  
Karthik. N ◽  
Keyword(s):  
Error Detection ◽  
High Performance ◽  
Cyclic Codes ◽  
Performance Error ◽  
Memory Applications

scholarly journals High-Performance and Energy-Efficient Fault Tolerance FPGA-to-FPGA Communication

2021 ◽  
Author(s):  
Naresh Kumar Reddy ◽  
Swamy Cherukuru ◽  
Veena Vani ◽  
Vishal Reddy
Keyword(s):  
Error Detection ◽  
High Speed ◽  
High Performance ◽  
Fault Tolerant ◽  
Key Factors ◽  
Error Detection And Correction ◽  
Performance Error ◽  
Increasing Demand ◽  
Accuracy Performance ◽  
Or Applications

Abstract These days, due to the increasing demand for high speed and parallel computation, several real world applications and systems include multiple FPGAs in them. Due to this, FPGAs often need to communicate among them. So, communication between the FPGAs is one of the key factors that determines the accuracy, performance and correctness of the entire multiple FPGAs systems or applications. This paper presents the design of an efficient multi-bit fault tolerant communication system for FPGA-to-FPGA communication. The proposed design is synthesized and also simulated through Vivado design suit 2018.3 and was communicated with two Kintex-7 FPGA boards. When compared with the existing FPGA-to-FPGA communication and inter FPGA communication designs, the proposed design have higher performance, error detection and correction capability.

scholarly journals Ab initio molecular dynamics and materials design for embedded phase-change memory

2021 ◽  
Vol 7 (1) ◽  
Author(s):  
Liang Sun ◽  
Yu-Xing Zhou ◽  
Xu-Dong Wang ◽  
Yu-Han Chen ◽  
Volker L. Deringer ◽  
...  
Keyword(s):  
Phase Change ◽  
High Performance ◽  
Materials Design ◽  
Atomic Scale ◽  
Ab Initio Molecular Dynamics ◽  
Core Material ◽  
Structure Property ◽  
Switching Speed ◽  
Atomic Structures ◽  
Memory Applications

AbstractThe Ge2Sb2Te5 alloy has served as the core material in phase-change memories with high switching speed and persistent storage capability at room temperature. However widely used, this composition is not suitable for embedded memories—for example, for automotive applications, which require very high working temperatures above 300 °C. Ge–Sb–Te alloys with higher Ge content, most prominently Ge2Sb1Te2 (‘212’), have been studied as suitable alternatives, but their atomic structures and structure–property relationships have remained widely unexplored. Here, we report comprehensive first-principles simulations that give insight into those emerging materials, located on the compositional tie-line between Ge2Sb1Te2 and elemental Ge, allowing for a direct comparison with the established Ge2Sb2Te5 material. Electronic-structure computations and smooth overlap of atomic positions (SOAP) similarity analyses explain the role of excess Ge content in the amorphous phases. Together with energetic analyses, a compositional threshold is identified for the viability of a homogeneous amorphous phase (‘zero bit’), which is required for memory applications. Based on the acquired knowledge at the atomic scale, we provide a materials design strategy for high-performance embedded phase-change memories with balanced speed and stability, as well as potentially good cycling capability.

A RECONFIGURATION TECHNIQUE FOR RELIABLE VLSI DSP ARRAY PROCESSORS

1992 ◽  
Vol 02 (03) ◽  
pp. 281-304
Author(s):  
SANJAY P. POPLI ◽  
MAGDY A. BAYOUMI ◽  
AKASH TYAGI
Keyword(s):  
Fault Tolerance ◽  
Error Detection ◽  
High Performance ◽  
Interconnection Network ◽  
Digital Signal ◽  
Design Criterion ◽  
Fault Detection And Diagnosis ◽  
Detection Technique ◽  
Concurrent Error Detection ◽  
Tolerance Strategy

Real-time digital signal processing (DSP) applications require high performance parallel architectures that are also reliable. VLSI arrays are good candidates for providing the required high throughput for these applications. These arrays which consist of a number of regularly interconnected processing elements (PEs) will not function correctly in the presence of even a single fault in any of the PEs. Fault tolerance has therefore become a vital design criterion for VLSI arrays. In this paper, a fault tolerance strategy for VLSI arrays is proposed, which significantly improves the reliability of the system. The fault tolerance scheme is composed of two phases: testing and locating faults (fault detection and diagnosis), and reconfiguration. The first phase employs an on-line error detection technique which achieves a compromise between the space and time redundancy approaches. This concurrent error detection technique reduces the rollback time considerably. The reconfiguration phase is achieved by using a global control responsible for changing the states of the switches in the interconnection network. Backtracking is introduced into the algorithm for maximizing the processor utilization, at the same time keeping the complexity of the interconnection network as simple as possible. Finally, a reliability analysis of this scheme using a Markov model and a comparison with some previous schemes are given.

Performance of IEEE 802.11n LDPC codes

2017 ◽  
Vol 11 (22) ◽  
pp. 1065-1073
Author(s):  
Yenny Alexandra Avendano Martinez ◽  
Octavio Jose Salcedo Parra ◽  
Giovanny Mauricio Tarazona Bermudez
Keyword(s):  
Error Detection ◽  
High Performance ◽  
Ldpc Codes ◽  
Low Density ◽  
Parity Check ◽  
Ieee 802.11N ◽  
Noise Environment ◽  
Low Density Parity Check ◽  
Parity Check Codes

LDPC (Low Density Parity Check Codes) is a set of algorithms that send, receive and correct in a noise environment, frames transmitted in a LAN environment. This article demonstrates the high performance of the LDPC in environments of noise, compared to the CRC error detection code highly currently implemented, in this way the efficiency of LDPC is shown specifically over the 802. 11n protocol.

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