The Twelfth International Symposium on High-Performance Computer Architecture, 2006.
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Efficient Instruction Schedulers for SMT Processors

The Twelfth International Symposium on High-Performance Computer Architecture, 2006. ◽

10.1109/hpca.2006.1598137 ◽

2006 ◽

Cited By ~ 8

Author(s):

J.J. Sharkey ◽

D.V. Ponomarev

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Reducing Resource Redundancy for Concurrent Error Detection Techniques in High Performance Microprocessors

The Twelfth International Symposium on High-Performance Computer Architecture, 2006. ◽

10.1109/hpca.2006.1598130 ◽

2006 ◽

Cited By ~ 13

Author(s):

S. Kumar ◽

A. Aggarwal

Keyword(s):

Error Detection ◽

High Performance ◽

Concurrent Error Detection ◽

Detection Techniques

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Industrial Perspectives: The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip Bandwidth

The Twelfth International Symposium on High-Performance Computer Architecture, 2006. ◽

10.1109/hpca.2006.1598128 ◽

2006 ◽

Author(s):

P. Emma

Keyword(s):

Storage Capacity ◽

On Chip

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A Decoupled KILO-Instruction Processor

The Twelfth International Symposium on High-Performance Computer Architecture, 2006. ◽

10.1109/hpca.2006.1598112 ◽

2006 ◽

Cited By ~ 19

Author(s):

M. Pericas ◽

A. Cristal ◽

R. Gonzalez ◽

D.A. Jimenez ◽

M. Valero

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DMA-Aware Memory Energy Management

The Twelfth International Symposium on High-Performance Computer Architecture, 2006. ◽

10.1109/hpca.2006.1598120 ◽

2006 ◽

Cited By ~ 27

Author(s):

V. Pandey ◽

Weihang Jiang ◽

Yuanyuan Zhou ◽

R. Bianchini

Keyword(s):

Energy Management

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Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM

The Twelfth International Symposium on High-Performance Computer Architecture, 2006. ◽

10.1109/hpca.2006.1598122 ◽

2006 ◽

Cited By ~ 100

Author(s):

R.K. Venkatesan ◽

S. Herr ◽

E. Rotenberg

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Construction and Use of Linear Regression Models for Processor Performance Analysis

The Twelfth International Symposium on High-Performance Computer Architecture, 2006. ◽

10.1109/hpca.2006.1598116 ◽

2006 ◽

Cited By ~ 79

Author(s):

P.J. Joseph ◽

K. Vaswani ◽

M.J. Thazhuthaveetil

Keyword(s):

Performance Analysis ◽

Linear Regression ◽

Regression Models ◽

Linear Regression Models ◽

Processor Performance

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Software-Hardware Cooperative Memory Disambiguation

The Twelfth International Symposium on High-Performance Computer Architecture, 2006. ◽

10.1109/hpca.2006.1598133 ◽

2006 ◽

Cited By ~ 4

Author(s):

R. Huang ◽

A. Garg ◽

M. Huang

Keyword(s):

Memory Disambiguation

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Speculative Synchronization and Thread Management for Fine Granularity Threads

The Twelfth International Symposium on High-Performance Computer Architecture, 2006. ◽

10.1109/hpca.2006.1598136 ◽

2006 ◽

Cited By ~ 2

Author(s):

A. Gontmakher ◽

A. Mendelson ◽

A. Schuster ◽

G. Shklover

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Industrial Perspectives: Platform Design Challenges with Many cores

The Twelfth International Symposium on High-Performance Computer Architecture, 2006. ◽

10.1109/hpca.2006.1598126 ◽

2006 ◽

Cited By ~ 1

Author(s):

R. Yavatkar

Keyword(s):

Platform Design ◽

Design Challenges

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The Twelfth International Symposium on High-Performance Computer Architecture, 2006.Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Efficient Instruction Schedulers for SMT Processors

Reducing Resource Redundancy for Concurrent Error Detection Techniques in High Performance Microprocessors

Industrial Perspectives: The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip Bandwidth

A Decoupled KILO-Instruction Processor

DMA-Aware Memory Energy Management

Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM

Construction and Use of Linear Regression Models for Processor Performance Analysis

Software-Hardware Cooperative Memory Disambiguation

Speculative Synchronization and Thread Management for Fine Granularity Threads

Industrial Perspectives: Platform Design Challenges with Many cores

The Twelfth International Symposium on High-Performance Computer Architecture, 2006.
Latest Publications