- Design of High-Performance Error-Correcting Codes Using FPGA

2018 ◽  
pp. 380-403
Keyword(s):  
High Performance ◽  
Error Correcting Codes ◽  
Performance Error

scholarly journals Application-based fault tolerance techniques for sparse matrix solvers

2017 ◽  
Vol 32 (5) ◽  
pp. 627-640
Author(s):  
Simon McIntosh–Smith ◽  
Rob Hunt ◽  
James Price ◽  
Alex Warwick Vesztrocy
Keyword(s):  
Fault Tolerance ◽  
High Performance Computing ◽  
High Performance ◽  
Sparse Matrix ◽  
Sparse Matrices ◽  
Error Correcting Codes ◽  
Computing Systems ◽  
Hardware Costs ◽  
Extreme Scale ◽  
Performance Computing

High-performance computing systems continue to increase in size in the quest for ever higher performance. The resulting increased electronic component count, coupled with the decrease in feature sizes of the silicon manufacturing processes used to build these components, may result in future exascale systems being more susceptible to soft errors caused by cosmic radiation than in current high-performance computing systems. Through the use of techniques such as hardware-based error-correcting codes and checkpoint-restart, many of these faults can be mitigated at the cost of increased hardware overhead, run-time, and energy consumption that can be as much as 10–20%. Some predictions expect these overheads to continue to grow over time. For extreme scale systems, these overheads will represent megawatts of power consumption and millions of dollars of additional hardware costs, which could potentially be avoided with more sophisticated fault-tolerance techniques. In this paper we present new software-based fault tolerance techniques that can be applied to one of the most important classes of software in high-performance computing: iterative sparse matrix solvers. Our new techniques enables us to exploit knowledge of the structure of sparse matrices in such a way as to improve the performance, energy efficiency, and fault tolerance of the overall solution.

scholarly journals CD-ROM system using high performance error correcting system.

1986 ◽  
Vol 40 (6) ◽  
pp. 501-507 ◽  
Author(s):  
Takashi Takeuchi ◽  
Tamotsu Ito ◽  
Tadashi Saito ◽  
Takashi Hoshino ◽  
Hiroo Okamoto ◽  
...  
Keyword(s):  
High Performance ◽  
Cd Rom ◽  
Performance Error

ANALYSIS AND DESIGN OF AN ABFT AND PARITY-CHECKING TECHNIQUE IN HIGH PERFORMANCE COMPUTING SYSTEMS

2012 ◽  
Vol 21 (03) ◽  
pp. 1250017 ◽  
Author(s):  
HODJAT HAMIDI ◽  
ABBAS VAFAEI ◽  
SEYED AMIRHASSAN MONADJEMI
Keyword(s):  
High Performance Computing ◽  
High Performance ◽  
Input Data ◽  
Error Correcting Codes ◽  
Threshold Detector ◽  
Computing Systems ◽  
Analysis And Design ◽  
Processing Block ◽  
Processing Errors ◽  
Performance Computing

We present a new approach to algorithm-based fault tolerance (ABFT) and parity-checking techniques in the design of high performance computing systems. The ABFT technique employs real convolution error-correcting codes to encode the input data. In order to reduce the round-off error from the output decoding process, systematic real convolution encoding is employed. This paper proposes an efficient method to detect the arithmetic errors using convolution codes at the output compared with an equivalent parity value derived from the input data. Number data processing errors are detected by comparing parity values associated with a convolution code. These comparable sets will be very close numerically, although not identical because of round-off error differences between the two parity generation processes. The effects of internal failures and round-off error are modeled by additive error sources located at the output of the processing block and input at threshold detector. This model combines the aggregate effects of errors and applies them to the respective outputs.

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