scholarly journals Threshold voltage analytical model for strained Si SOI MOSFET with high-k dielectric

2010 ◽  
Vol 59 (11) ◽  
pp. 8131
Author(s):  
Li Jin ◽  
Liu Hong-Xia ◽  
Li Bin ◽  
Cao Lei ◽  
Yuan Bo
Keyword(s):  
Analytical Model ◽  
Threshold Voltage ◽  
Strained Si ◽  
Soi Mosfet ◽  
High K ◽  
High K Dielectric

scholarly journals High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

2021 ◽  
Author(s):  
Prashant Kumar ◽  
Munish Vashishath ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Low Power ◽  
Analytical Model ◽  
Threshold Voltage ◽  
Figure Of Merit ◽  
Double Gate ◽  
Short Channel ◽  
Ultra Low Power ◽  
High K ◽  
Channel Effects ◽  
High K Dielectric

Abstract This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson’s equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29% improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

scholarly journals Threshold voltage and DIBL effect analysis and modeling for FD-SOI MOSFET with high k + SiO$_2$ gate

2019 ◽  
Vol 49 (3) ◽  
pp. 342-360
Author(s):  
Luxu WAN ◽  
Jianguo YANG ◽  
Daoming KE ◽  
Di WU ◽  
Fei YANG ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Effect Analysis ◽  
Soi Mosfet ◽  
High K

scholarly journals 2-D analytical modeling of dual material gate fully depleted SOI MOSFET with high-k dielectric

2008 ◽  
Vol 57 (6) ◽  
pp. 3807
Author(s):  
Luan Su-Zhen ◽  
Liu Hong-Xia ◽  
Jia Ren-Xu ◽  
Cai Nai-Qiong
Keyword(s):  
Analytical Modeling ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
High K ◽  
High K Dielectric ◽  
Dual Material

scholarly journals Analytical Model for the SOI Lateral Power Device With Step Width Technique and High-${k}$ Dielectric

2019 ◽  
Vol 66 (7) ◽  
pp. 3055-3059 ◽  
Author(s):  
Jiafei Yao ◽  
Yufeng Guo ◽  
Kemeng Yang ◽  
Lin Du ◽  
Jun Zhang ◽  
...  
Keyword(s):  
Analytical Model ◽  
Power Device ◽  
Step Width ◽  
High K ◽  
High K Dielectric

Interface Trap Charge Induced Threshold Voltage Modeling of WFE High-K SOI MOSFET

Silicon ◽  
2020 ◽  
Vol 12 (12) ◽  
pp. 2893-2900
Author(s):  
Priyanka Saha ◽  
Pritha Banerjee ◽  
Dinesh Kumar Dash ◽  
Subir Kumar Sarkar
Keyword(s):  
Threshold Voltage ◽  
Interface Trap ◽  
Trap Charge ◽  
Soi Mosfet ◽  
High K
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