scholarly journals Analysis of the back-gate effect on the breakdown behavior of lateral high-voltage SOI transistors

2007 ◽  
Vol 56 (7) ◽  
pp. 3990
Author(s):  
Qiao Ming ◽  
Zhang Bo ◽  
Li Zhao-Ji ◽  
Fang Jian ◽  
Zhou Xian-Da
Keyword(s):  
2005 ◽  
Vol 52 (7) ◽  
pp. 1649-1655 ◽  
Author(s):  
S. Schwantes ◽  
T. Florian ◽  
T. Stephan ◽  
M. Graf ◽  
V. Dudek

Author(s):  
Stefan Schwantes ◽  
Josef Furthaler ◽  
Bernd Schauwecker ◽  
Franz Dietz ◽  
Michael Graf ◽  
...  

2006 ◽  
Vol 6 (3) ◽  
pp. 377-385 ◽  
Author(s):  
S. Schwantes ◽  
J. Furthaler ◽  
B. Schauwecker ◽  
F. Dietz ◽  
M. Graf ◽  
...  

2003 ◽  
Vol 24 (6) ◽  
pp. 414-416 ◽  
Author(s):  
V. Kilchytska ◽  
D. Levacq ◽  
D. Lederer ◽  
J.-P. Raskin ◽  
D. Flandre

2015 ◽  
Vol 62 (4) ◽  
pp. 1098-1104 ◽  
Author(s):  
Xin Zhou ◽  
Ming Qiao ◽  
Yitao He ◽  
Zhuo Wang ◽  
Zhaoji Li ◽  
...  
Keyword(s):  

2017 ◽  
Vol 30 (4) ◽  
pp. 627-638 ◽  
Author(s):  
Alexandru-Mihai Antonescu ◽  
Lidia Dobrescu

The present work proposes an innovative circuit that is able to compensate the inverter switching point voltage variation due to supply voltage change. The circuit is designed to work for a 1.6V to 2V supply voltage range. The operation principle includes the back gate effect and an original transistor switching.


2017 ◽  
Author(s):  
T. Hoshii ◽  
R. Takayama ◽  
A. Nakajima ◽  
S. Nishizawa ◽  
H. Ohashi ◽  
...  
Keyword(s):  

2016 ◽  
Vol 25 (01n02) ◽  
pp. 1640005 ◽  
Author(s):  
Antoine Litty ◽  
Sylvie Ortolland ◽  
Dominique Golanski ◽  
Christian Dutto ◽  
Alexandres Dartigues ◽  
...  

High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides RESURF-like effect (reduced surface field) and offers additional flexibility for HVMOS integration directly in the ultrathin film of the FDSOI wafer. In this configuration, the primary back-gate controls the threshold voltage (VTH) to ensure performance and low leakage current. The second back-gate, located underneath the drift region, acts as a field plate enabling the improvement of the ON resistance (RON) and breakdown voltage (BV). The trade-off RON.S versus BV is investigated as a function of doping level, length and thickness of the drift region. We report promising results and discuss further developments for successful integration of high-voltage MOSFETs in ultrathin CMOS FDSOI technology.


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