scholarly journals The Decomposition of DSP’s Control Logic Block for Power Reduction

2012 ◽  
Vol 16 (1) ◽  
Author(s):  
Borisav Jovanovic ◽  
Milunka Damnjanović
Keyword(s):  
Power Reduction ◽  
Control Logic ◽  
Logic Block

Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC

2017 ◽  
Vol 26 (05) ◽  
pp. 1750077 ◽  
Author(s):  
Anush Bekal ◽  
Shabi Tabassum ◽  
Manish Goswami
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Digital Control ◽  
Low Power Design ◽  
Cmos Technology ◽  
Control Logic ◽  
Control Block ◽  
Logic Block ◽  
External Clock ◽  
Asynchronous Sar

The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of the external clock pulse. The outputs from the comparator are given to a XOR logic whose outputs serve as an internally generated clock (ready signal) to trigger the digital control block. Hence, an external clock is not required to initiate the digital control block making its operation asynchronous. By implementing this, the ADC can circumvent the usage of an oversampled clock and can operate on a single low-speed sample clock. This, in turn, saves power and it cuts down the required resilience in sampling rates. The proposed ADC has been designed and simulated using UMC-0.18[Formula: see text][Formula: see text]m CMOS technology which dissipates 32.18[Formula: see text][Formula: see text]W power when operated on a single 1[Formula: see text]V power supply and achieves complete 8-bit conversion in 1.09[Formula: see text][Formula: see text]s. The relative accuracy of capacitor ratio, aperture jitter and FOM are 0.39[Formula: see text], 1.2[Formula: see text]ns and 125[Formula: see text]fJ/conversion-step, respectively.

scholarly journals Efficient Design of Control Logic Block in Dual Port Memory

2020 ◽  
Vol 8 (6) ◽  
pp. 841-845
Keyword(s):  
Efficient Design ◽  
Memory Location ◽  
Control Logic ◽  
Lower Priority ◽  
Read Operation ◽  
Logic Block ◽  
Sram Cell ◽  
A Priority ◽  
Data Priority

A dual port memory in QCA are a study of data in different ports, but the data conflicts are very difficult to identify. Dual port memory is mainly focused on the data priority. It can be generated from the design of the control logic block. Priority bit are used, where both ports access the same memory location. Dual port memory functionality can be identified with a priority bit. When the port having the same memory location, only the port having the high priority is selected and other port are discarded. But when the read operation are requested to both the ports at same locations, having no conflicts and both the ports are requested to perform read operations. Data conflicts on the SRAM cell can be overcome by discarding the lower priority completely. Priorities are defined in terms of the area and delay. The idea behind this work is to minimize the area and delay in the dual port memory and proposed a multilayer Cross-Over design to provide an efficiency to the dual port memory and simulation result of design are shown in QCA Designer Tool-2.0.

A Novel Compiler Assisted Approach for Issue Queue Power Reduction

2014 ◽  
Vol 543-547 ◽  
pp. 1981-1986
Author(s):  
Peng Wei Lv ◽  
Jian Qing Xiao ◽  
Sen Mao Shi
Keyword(s):  
Energy Consumption ◽  
Power Dissipation ◽  
Power Reduction ◽  
Instruction Level Parallelism ◽  
Superscalar Processors ◽  
Control Logic ◽  
Complex Control ◽  
Compiler Analysis ◽  
Static Power ◽  
Level Parallelism

Superscalar processors contain complex control logic in order to extract sufficient instruction level parallelism (ILP). The issue logic is one of the main sources of power dissipation in current superscalar processors. It has been estimated that up to 30% of the energy consumed by a processor is in the issue logic. This paper presents a novel compiler assisted approach to power reduction where we use compiler analysis to pass information to the processor about the number of entries needed, allowing the processor to resize the issue queue dynamically which limit the number of instruction dispatched and resident in the queue reduces the energy consumption without adversely affecting performance. Compared with hardware scheme, our approach is simpler faster and saves more energy. Using the approach we achieve 43.3% dynamic and 28.5% static power savings.

scholarly journals Technique to Dynamically Reconfigure FPGAs using Control Registers

2019 ◽  
Vol 9 (1S3) ◽  
pp. 117-121
Keyword(s):  
Fault Tolerant ◽  
Ballistic Transport ◽  
Processing System ◽  
Power Reduction ◽  
Programmable Logic ◽  
Virtual Source ◽  
Logic Device ◽  
Improve Performance ◽  
Programmable Logic Device ◽  
Logic Block

Due to increased use of FPGAs computation intensive applications, the need for embedded processing system integrated with programmable logic device has also increased. Configuration of programmable logic device by the processing system through its interface improves the efficiency of the device. In order to operate as a stand-alone device and to have a better efficiency, the programmable logic device must be capable of dynamically programming its own configuration memory. In this paper, we propose a configurable logic block with a control register to improve performance of the programmable logic device. The control register acts like a decentralized configuration memory array which can be programmed by other such configurable logic blocks. The FPGAs are fault tolerant devices with repetitive structures requiring high packaging density. This property of FPGA enables the use of CNTFETs for design of FPGAs. CNTFETs offer high trans-conductance and 1-D ballistic transport of electrons and holes which minimizes the power consumed by the FPGA. The proposed control register based architecture was implemented using Cadence Virtuoso using virtual source CNTFET model from Stanford University. A power reduction of 17.62% is achieved using CNTFETs when compared with FINFET at same technology node and the architecture was verified for various configurations of the control register

LEAKAGE POWER REDUCTION USING MULTI MODAL DRIVEN HIERARCHICAL POWER MODE SWITCHES

2018 ◽  
Vol 6 (2) ◽  
pp. 1
Author(s):  
SEKHAR REDDY M. CHANDRA ◽  
REDDY P. RAMANA ◽  
◽  
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Power Mode

Stand-by Power Reduction Using Experimentally Demonstrated Nano-Electromechanical Switch in CMOS Technologies

2020 ◽  
pp. 1-7
Author(s):  
Sumit Saha ◽  
Arpit Singh ◽  
Maryam Shojaei Baghini ◽  
Mayank Goel ◽  
V. Ramgopal Rao
Keyword(s):  
Power Reduction

scholarly journals A Coordinated Control of Offshore Wind Power and BESS to Provide Power System Flexibility

Energies ◽  
2021 ◽  
Vol 14 (15) ◽  
pp. 4650
Author(s):  
Martha N. Acosta ◽  
Francisco Gonzalez-Longatt ◽  
Juan Manuel Roldan-Fernandez ◽  
Manuel Burgos-Payan
Keyword(s):  
Energy Storage ◽  
Power System ◽  
Wind Power ◽  
Single Layer ◽  
Coordinated Control ◽  
Test System ◽  
Power Converter ◽  
Control Logic ◽  
Battery Energy Storage ◽  
Battery Energy

The massive integration of variable renewable energy (VRE) in modern power systems is imposing several challenges; one of them is the increased need for balancing services. Coping with the high variability of the future generation mix with incredible high shares of VER, the power system requires developing and enabling sources of flexibility. This paper proposes and demonstrates a single layer control system for coordinating the steady-state operation of battery energy storage system (BESS) and wind power plants via multi-terminal high voltage direct current (HVDC). The proposed coordinated controller is a single layer controller on the top of the power converter-based technologies. Specifically, the coordinated controller uses the capabilities of the distributed battery energy storage systems (BESS) to store electricity when a logic function is fulfilled. The proposed approach has been implemented considering a control logic based on the power flow in the DC undersea cables and coordinated to charging distributed-BESS assets. The implemented coordinated controller has been tested using numerical simulations in a modified version of the classical IEEE 14-bus test system, including tree-HVDC converter stations. A 24-h (1-min resolution) quasi-dynamic simulation was used to demonstrate the suitability of the proposed coordinated control. The controller demonstrated the capacity of fulfilling the defined control logic. Finally, the instantaneous flexibility power was calculated, demonstrating the suitability of the proposed coordinated controller to provide flexibility and decreased requirements for balancing power.

Optimizing FPGA logic block architectures for self-repairing hardened arithmetic

2021 ◽  
Author(s):  
A. Valanarasi ◽  
S.M.H. SithiShameem Fathima ◽  
C. Priya ◽  
B. Babu Mohan ◽  
J. Preethipilomina ◽  
...  
Keyword(s):  
Logic Block
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