Actuator power reduction using L-C oscillator circuits

2000 ◽  
Author(s):  
Jayant Sirohi ◽  
Inderjit Chopra
Keyword(s):  
Power Reduction ◽  
Oscillator Circuits

LEAKAGE POWER REDUCTION USING MULTI MODAL DRIVEN HIERARCHICAL POWER MODE SWITCHES

2018 ◽  
Vol 6 (2) ◽  
pp. 1
Author(s):  
SEKHAR REDDY M. CHANDRA ◽  
REDDY P. RAMANA ◽  
◽  
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Power Mode

Stand-by Power Reduction Using Experimentally Demonstrated Nano-Electromechanical Switch in CMOS Technologies

2020 ◽  
pp. 1-7
Author(s):  
Sumit Saha ◽  
Arpit Singh ◽  
Maryam Shojaei Baghini ◽  
Mayank Goel ◽  
V. Ramgopal Rao
Keyword(s):  
Power Reduction

scholarly journals Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1587
Author(s):  
Duo Sheng ◽  
Hsueh-Ru Lin ◽  
Li Tai
Keyword(s):  
High Performance ◽  
Power Reduction ◽  
System On Chip ◽  
Timing Information ◽  
Multi Stage ◽  
Dynamic Voltage ◽  
And Performance ◽  
On Chip ◽  
Maximum Measurement ◽  
Maximum Measurement Error

High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.

scholarly journals Fault-Tolerant Control in a Peak-Power Reduction System of a Traction Substation with Multi-String Battery Energy Storage System

Energies ◽  
2021 ◽  
Vol 14 (15) ◽  
pp. 4565
Author(s):  
Marcin Szott ◽  
Marcin Jarnut ◽  
Jacek Kaniewski ◽  
Łukasz Pilimon ◽  
Szymon Wermiński
Keyword(s):  
Energy Storage ◽  
Peak Power ◽  
Fault Tolerant ◽  
Storage System ◽  
Energy Storage System ◽  
Power Reduction ◽  
Battery Energy Storage System ◽  
Battery Energy Storage ◽  
Traction Substation ◽  
Battery Energy

This paper introduces the concept of fault-tolerant control (FTC) of a multi-string battery energy storage system (BESS) in the dynamic reduction system of a traction substation load (DROPT). The major task of such a system is to reduce the maximum demand for contracted peak power, averaged for 15 min. The proposed concept, based on a multi-task control algorithm, takes into account: a three-threshold power limitation of the traction substation, two-level reduction of available power of a BESS and a multi-string structure of a BESS. It ensures the continuity of the maximum peak power demand at the contracted level even in the case of damage or disconnection of at least one chain of cells of the battery energy storage (BES) or at least one converter of the power conversion system (PCS). The proposed control strategy has been tested in a model of the system for dynamic reduction of traction substation load with a rated power of 5.5 MW. Two different BESS implementations have been proposed and several possible cases of failure of operations have been investigated. The simulation results have shown that the implementation of a multi-string BESS and an appropriate control algorithm (FTC) may allow for maintenance of the major assumption of DROPT, which is demanded power reduction (from 3.1 MW to 0.75 MW), even with a reduction of the BESS available power by at least 25% and more in the even in fault cases.

scholarly journals Neurophysiological and behavioural effects of conventional and high definition tDCS

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Fabio Masina ◽  
Giorgio Arcara ◽  
Eleonora Galletti ◽  
Isabella Cinque ◽  
Luciano Gamberini ◽  
...  
Keyword(s):  
Response Times ◽  
Power Reduction ◽  
Alpha Power ◽  
High Definition ◽  
Mixed Effect ◽  
State Dependency ◽  
Mixed Effect Models ◽  
Beta Power ◽  
Neurophysiological Data ◽  
Spectrum Density

AbstractHigh-definition transcranial direct current stimulation (HD-tDCS) seems to overcome a drawback of traditional bipolar tDCS: the wide-spread diffusion of the electric field. Nevertheless, most of the differences that characterise the two techniques are based on mathematical simulations and not on real, behavioural and neurophysiological, data. The study aims to compare a widespread tDCS montage (i.e., a Conventional bipolar montage with extracephalic return electrode) and HD-tDCS, investigating differences both at a behavioural level, in terms of dexterity performance, and a neurophysiological level, as modifications of alpha and beta power as measured with EEG. Thirty participants took part in three sessions, one for each montage: Conventional tDCS, HD-tDCS, and sham. In all the conditions, the anode was placed over C4, while the cathode/s placed according to the montage. At baseline, during, and after each stimulation condition, dexterity was assessed with a Finger Tapping Task. In addition, resting-state EEG was recorded at baseline and after the stimulation. Power spectrum density was calculated, selecting two frequency bands: alpha (8–12 Hz) and beta (18–22 Hz). Linear mixed effect models (LMMs) were used to analyse the modulation induced by tDCS. To evaluate differences among the montages and consider state-dependency phenomenon, the post-stimulation measurements were covariate-adjusted for baseline levels. We observed that HD-tDCS induced an alpha power reduction in participants with lower alpha at baseline. Conversely, Conventional tDCS induced a beta power reduction in participants with higher beta at baseline. Furthermore, data showed a trend towards a behavioural effect of HD-tDCS in participants with lower beta at baseline showing faster response times. Conventional and HD-tDCS distinctively modulated cortical activity. The study highlights the importance of considering state-dependency to determine the effects of tDCS on individuals.

scholarly journals Topology optimized thermoelectric generator: a parametric study

2021 ◽  
Vol 0 (0) ◽  
Author(s):  
John Mativo ◽  
Kevin Hallinan ◽  
Uduak George ◽  
Greg Reich ◽  
Robin Steininger
Keyword(s):  
Topology Optimization ◽  
Thermoelectric Generator ◽  
Volume Fraction ◽  
Power Conversion ◽  
Power Production ◽  
Power Reduction ◽  
Void Volume Fraction ◽  
Thermoelectric Generators ◽  
Maximal Power ◽  
Design Yield

Abstract Typical thermoelectric generator legs are brittle which limits their application in vibratory and shear environments. Research is conducted to develop compliant thermoelectric generators (TEGs) capable of converting thermal loads to power, while also supporting shear and vibratory loads. Mathematical structural, thermal, and power conversion models are developed. Topology optimization is employed to tailor the TEG design yield maximal power production while sustaining the applied shear and vibratory loads. As a specific example, results are presented for optimized TEG legs with a void volume fraction of 0.2 that achieve compliance shear displacement of 0.0636 (from a range of 0.0504 to 0.6079). In order to achieve the necessary compliance to support the load, the power reduction is reduced by 20% relative to similarly sized void free TEG legs.

Sign in / Sign up

Export Citation Format

Share Document