scholarly journals Técnicas de Tolerância a Falhas em uma Plataforma para Prototipagem Rápida Usando Microcontroladores

2019 ◽  
Author(s):  
Kleber Kruger ◽  
Fabio Iaione
Keyword(s):  
Fault Tolerance ◽  
Power Consumption ◽  
Rapid Prototyping ◽  
System Performance ◽  
Processing Time ◽  
Fault Tolerant ◽  
Weather Station ◽  
Fault Tolerant System ◽  
Sram Memory

This paper describes the implementation of fault tolerance techniques (based on data and processing redundancy) in programming of a rapid prototyping platform using microcontrollers. To evaluate performance of these techniques was used a fault injector software and a weather station system as a case study. Experiments simulated faults in sensor readings and faults in SRAM memory regions of the weather station. Finally, the fault-tolerant system performance is presented in comparison with non-fault-tolerant system, considering incidence of failures, processing time, memory and power consumption.

scholarly journals System Control In Fault And Normal Conditions Case Study - Quanser SRV-02

2015 ◽  
Vol 67 (1) ◽  
pp. 133-138
Author(s):  
Ionut Cristian Resceanu ◽  
Cristina Floriana Resceanu
Keyword(s):  
Fault Tolerance ◽  
Theoretical Analysis ◽  
Control Method ◽  
Fault Tolerant ◽  
Fault Tolerant Control ◽  
Control Law ◽  
System Control ◽  
Sensor Fault ◽  
Simulation Results

Abstract A fault tolerant control method is proposed for Quanser SRV-02 System in order to maintain the required performance in the presence of sensor failures. The proposed approach integrates control law and a sensor fault tolerance schema. Theoretical analysis and simulation results have confirmed the effectiveness of the proposed method.

scholarly journals Design of a Fault Tolerant Razor Flip Flop Sklansky Adder for Delay Reduction in FIR Filter

2019 ◽  
Vol 8 (9) ◽  
pp. 2647-2651
Keyword(s):  
Fault Tolerance ◽  
High Performance ◽  
Fault Tolerant ◽  
Digital Signal ◽  
Fir Filter ◽  
Delay Reduction ◽  
Flip Flop ◽  
Multiple Faults ◽  
Fault Tolerant System ◽  
Logic Unit

Basically, to reduce the failure rate in the system, we need to introduce the fault tolerant system. Because of multiple faults occurred in the system, the system will increase the area. To employ the adder architecture, different algorithms are used in digital signal processing. By introducing the fault tolerant system, the reliability of the proposed system will increase. So in this paper we introduced the design of fault tolerant razor flip flop using SKLANSKY adder for delay reduction in FIR filter. The razor flip flop will increase the energy efficiency of proposed system. This flip flop will store the information by latching the circuit. The SKLANSKY adder is the part of arithmetic logic unit. In proposed system, all bits are summed and followed to the fault tolerance system,. This fault tolerance system will detect the error and give efficient output. Hence compared to existed system, the proposed system gives high performance and accuracy in terms of delay.

scholarly journals Methods for building a high-performance fault-tolerant distributed database for the task of perimeter security

2021 ◽  
pp. 55-62
Author(s):  
Андрей Иванович Костюк ◽  
Наталия Михайловна Коробейникова
Keyword(s):  
Fault Tolerance ◽  
Performance Indicators ◽  
System Performance ◽  
High Performance ◽  
Fault Tolerant ◽  
Key Performance Indicators ◽  
Distributed Database ◽  
Security Problem ◽  
Key Indicators

Описаны методы построения высокопроизводительной отказоустойчивой распределенной базы данных для задачи охраны периметра. Представлена архитектура подсистемы отказоустойчивости, архитектура подсистемы резервного копирования, описаны подходы к достижению заданных ключевых показателей. Проведено исследование производительности системы, определены ключевые показатели эффективности, достигаемые подсистемой обеспечения отказоустойчивости. The paper discusses the methods for constructing a high-performance fault-tolerant distributed database for the perimeter security problem. The architecture of the fault tolerance subsystem, the architecture of the backup subsystem, and approaches to achieving the specified key indicators are described. The study of the system performance was carried out, the values of the key performance indicators achieved by the fault tolerance subsystem were determined.

scholarly journals Fault-tolerant architecture for Cache : Summaries, Assessments and Trends

2021 ◽  
Vol 2113 (1) ◽  
pp. 012068
Author(s):  
Xuru Wang ◽  
Xin Gao ◽  
Zongnan Liang ◽  
Jiawei Nian ◽  
Hongjin Liu
Keyword(s):  
Fault Tolerance ◽  
Power Consumption ◽  
Future Development ◽  
Fault Tolerant ◽  
Development Trend ◽  
The Other ◽  
Architecture Design ◽  
Related Research ◽  
Cache Architecture ◽  
The Future

Abstract Fault-tolerant design of cache is a key aspect of highly reliable processor design. In this paper, based on the key metrics in Cache architecture design: reliability, power consumption, latency and area, we divided the related research into two categories: one is to maximize reliability with guaranteed latency, power consumption and area, the other is to minimize latency, power consumption and area loss while ensuring fault tolerance reliability. Based on the classification, by analyzing different studies of Data and Tag in Cache, this paper gives the characteristics of these methods and the future development trend.

A CPN Based Method for Aspect-Oriented Modeling and Analysis of Fault Tolerance

2012 ◽  
Vol 457-458 ◽  
pp. 891-898
Author(s):  
Xiao Xing Sun ◽  
Hui Qun Yu ◽  
Hong Hao Liang
Keyword(s):  
Fault Tolerance ◽  
Fault Tolerant ◽  
Aspect Oriented Programming ◽  
Modeling And Analysis ◽  
Cpn Tools ◽  
Tolerance Modeling ◽  
Software Fault Tolerance ◽  
Implementation Level ◽  
Aspect Oriented Modeling

Software fault tolerance makes system complicated by means of diverse fault-tolerant mechanisms. Aspect-oriented programming has been confirmed as a well suited candidate to ease the problem. However, most of the existing works only focus on implementation level. This paper proposes an AOFTM model for aspect-oriented fault tolerance modeling with Coloured Petri nets at design level. Moreover, the weaving mechanism formally defined conducts the way to derive a woven net from AOFTM. A case study presents how AOFTM works, and its properties are analyzed using the CPN Tools.

scholarly journals A Case Study of Self-Checking Circuits Reliability

VLSI Design ◽  
1998 ◽  
Vol 5 (4) ◽  
pp. 373-383 ◽  
Author(s):  
Jien-Chung Lo
Keyword(s):  
Fault Tolerant ◽  
The Self ◽  
Hardware Complexity ◽  
Error Handling ◽  
Fault Tolerant System ◽  
Trade Offs ◽  
Self Testing

In this paper, we analyze the reliability of self-checking circuits. A case study is presented in which a fault-tolerant system with duplicated self-checking modules is compared to the TMR version. It is shown that a duplicated self-checking system has a much higher reliability than that of the TMR counterpart. More importantly, the reliability of the self-checking system does not drop as sharply as that of the TMR version. We also demonstrate the trade-offs between hardware complexity and error handling capability of self-checking circuits. Alternative self-checking designs where some hardware redundancies are removed with the lost of fault-secure and/or self-testing properties are also studied.

scholarly journals ANALISA PERBANDINGAN QUERY PENCARIAN MENGGUNAKAN FUNGSI MATCH-AGAINST PADA MYSQL DENGAN TABEL KAMUS

CCIT Journal ◽  
2018 ◽  
Vol 11 (1) ◽  
pp. 15-25
Author(s):  
Zudha Pratama ◽  
Yans Safarid Hudha ◽  
M Lukman Prayoghi
Keyword(s):  
Fault Tolerance ◽  
Search Engine ◽  
Digital Library ◽  
Processing Time ◽  
Fault Tolerant ◽  
The Other ◽  
Comparison Process ◽  
Search Query ◽  
Search Function ◽  
Complex Algorithm

Virtually all database-related systems provide search features. Starting from a complex search engine like google to a relatively simple example of search features on a digital library page. A good search engine is capable of delivering fast, accurate, and fault-tolerant results. Speed ​​may be affected by server device capabilities and complex algorithm combinations.The form of the condition condition used in the search query generally uses LIKE for partial search, REGEXP for multi key search, and MATCH-AGAINST for multi key search with fulltext index. However, these functions are not sufficient to perform a search selection on a slightly wrong key or rather fault tolerance that is still not good. So researchers do an analysis if one of the search function is combined with a dictionary table.Table dictionary as a comparator key to find a more appropriate key if key wrong key. But on the other hand the addition of the comparison process is estimated to have a weakness to the processing time. Researchers assume if the weakness can be overcome if the ability of the server is improved.

scholarly journals Fault Injection on a Mixed-Signal Programmable SoC with Design Diversity Mitigation

2016 ◽  
Vol 11 (3) ◽  
pp. 185-191
Author(s):  
Carlos J. G. Aguilera ◽  
Cristiano P. Chenet ◽  
Tiago R. Balen
Keyword(s):  
Fault Tolerant ◽  
Fault Injection ◽  
Random Sequence ◽  
Masking Effect ◽  
Mixed Signal ◽  
Sram Memory ◽  
On Chip ◽  
Sequence Generator ◽  
Design Diversity

This paper presents an approach for runtime software-based fault injection, applied to a commercial mixed-signal programmable system-on-chip (PSoC). The fault-injection scheme is based on a pseudo-random sequence generator and software interruption. A fault tolerant data acquisition system, based on a design diversity redundant scheme, is considered as case study. The fault injection is performed by intensively inserting bit flips in the peripherals control registers of the mixed-signal PSoC blocks, as well as in the SRAM memory of the device. Results allow to evaluate the applied fault tolerance technique, indicating that the system is able to tolerate most of the generated errors. Additionally, a high fault masking effect is observed, and different criticality levels are observed for faults injected into the SRAM memory and in the peripherals control registers.

Design of FPGA-Based Fault-Tolerant Embedded System

2012 ◽  
Vol 546-547 ◽  
pp. 1574-1579
Author(s):  
Zhi Wen Xiong ◽  
Wen Feng Wang ◽  
Hong Zeng
Keyword(s):  
Fault Tolerance ◽  
Embedded Systems ◽  
Embedded System ◽  
Fault Tolerant ◽  
Design Method ◽  
Data Acquisition System ◽  
Fault Tolerant System ◽  
System Developer ◽  
Hardware Faults ◽  
Adaptive Ability

Fault tolerant is one of major requirements for embedded systems. As the embedded systems become more and more complex, more chances for various fault. When design embedded system developer has to handle these faults. Before handling faults designer has to identify and understand the types and nature of faults.Faults is the sources for low dependability, faults can be hardware and software. Hardware faults can be distinguished from systematic faults like software or design errors. The Fault can be deleted, such as extensive testing or formal verification and tolerated by fault tolerance techniques. We restrict ourselves to the problem of fault tolerance and refer to other methods for troubleshooting.This paper discusses a new design method about the fault tolerant system of embedded system. We designed a fault tolerant system of data acquisition system in dynamically re-configurable FPGA. The experiment results show that the system not only be able to higher self-adaptive ability and reliability, but also can Through the FGPA to complete a specific algorithm.

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