A framework for high-speed parallel-prefix adder performance evaluation and comparison

2014 ◽  
Vol 43 (10) ◽  
pp. 1474-1490
Author(s):  
Richard F. Hobson
Keyword(s):  
Performance Evaluation ◽  
High Speed ◽  
Parallel Prefix ◽  
Performance Evaluation And Comparison ◽  
Prefix Adder

Design of high-speed low-power parallel-prefix adder trees in nanometer technologies

2013 ◽  
Vol 42 (7) ◽  
pp. 731-743 ◽  
Author(s):  
Stefania Perri ◽  
Marco Lanuzza ◽  
Pasquale Corsonello
Keyword(s):  
Low Power ◽  
High Speed ◽  
Parallel Prefix ◽  
Prefix Adder

scholarly journals Performance Evaluation of New Adder Designed for Electronic Circuits

2019 ◽  
Vol 8 (3) ◽  
pp. 5039-5043
Keyword(s):  
Performance Evaluation ◽  
Power Consumption ◽  
Digital System ◽  
Efficient Design ◽  
Electronic Circuits ◽  
Parallel Prefix ◽  
The Many ◽  
Prefix Adder ◽  
Logic Unit

Arithmetic and Logic Unit (ALU) is the important module in any digital system utilized in the current world applications. Adder plays major role in the construction of any ALU. Multipliers can also be designed with the help of continuous addition. The efficient design of adders is very much needed for the efficient ALU design. Parallel prefix adder has been chosen in this research because of its fastest computation and efficiency. Kogge Stone, Sklansky, Ladner Fischer, Brunt Kung, Han-Carlson and Knowles are the adders discussed in this research. Further, the combinations of any two adders have also been tested for the best efficiency in terms of power consumption and delay utilisation. From the many combinations, it is found that the proposed combination of Bruntkung and SKlansky (BSK) adder performs excellent with the power consumption of 25011.22 nW and delay of 1243 pS.

scholarly journals Design a High Speed Multiplier using Two Phase PPA

2019 ◽  
Vol 8 (11S2) ◽  
pp. 146-149
Keyword(s):  
High Speed ◽  
Two Phase ◽  
Ripple Carry Adder ◽  
Product Generation ◽  
Different Types ◽  
Effective System ◽  
Parallel Prefix ◽  
Three Stages ◽  
Prefix Adder ◽  
Prefix Adders

Basically, multiplier is an efficient superconductor logic which performs various switching operation. Here different types of adders are analysed using different methodologies. In this paper we introduced a multiplier using proposed PPA. It uses parallel prefix adders in their reduction phase and it is an effective system for faster results and optimised. The entire operation of proposed system depends upon three stages they are multiplier partial product generation, reduction stages and parallel prefix adder which is discussed in below sections. The delay gets reduced by achieving low logical depth in the system. So the Proposed system reduces the delay. From the proposed system we can observe that there is a reduction in delay and complexity. Compared to ripple carry adder and carry save adder, proposed system gives better results.

scholarly journals Design of High Speed Advanced Encryption Standard using PPA and PPM

2019 ◽  
Vol 8 (9) ◽  
pp. 2679-2684
Keyword(s):  
High Speed ◽  
Block Cipher ◽  
Internet Security ◽  
Advanced Encryption Standard ◽  
Aes Algorithm ◽  
Fundamental Goal ◽  
Parallel Prefix ◽  
Encoding Strategies ◽  
Prefix Adder ◽  
Symmetric Block

Basically, internet security plays crucial role in past three decades. So in worldwide Advanced Encryption Standard (AES) algorithm is used. AES consists of symmetric block cipher blocks. In this paper we proposed the simplified AES algorithm (S-DES) using parallel prefix adder (PPA) and parallel prefix multiplier (PPM). This parallel prefix adder and parallel prefix multiplier will generate a product formed by multiplying the multiplicand. This algorithm possess specific structure to encrypt and decrypt delicate information and is connected in equipment and programming everywhere throughout the world. It is amazingly hard to programmers to get the genuine information while encoding the AES calculation. The fundamental goal of this algorithm is to build up a model that is executed for correspondence reason, and to test the created model regarding precision reason. The encryption procedure comprises the mix of different traditional methods, for example, substitution, improvement and change encoding strategies. At last the key extension module will comprise the quantity of iterative preparing rounds so as to expand its resistance against unapproved assaults.

scholarly journals Design and Implementation of High Speed Area Efficient Carry Select Adder Using Spanning Tree Adder Technique

2018 ◽  
pp. 21-26
Author(s):  
Hima Bindu Vykuntam ◽  
Chennaiah M ◽  
Sudhakar K
Keyword(s):  
Spanning Tree ◽  
High Speed ◽  
Computation Time ◽  
Digital Design ◽  
Comparative Performance ◽  
Ripple Carry Adder ◽  
Parallel Prefix ◽  
Carry Select Adder ◽  
Prefix Adder ◽  
Prefix Adders

In this paper, we propose Carry Select Adder (CSLA) architecture with parallel prefix adder. Instead of using 4-bit Brent Kung Adder (BKA), another parallel prefix adder i.e., 4-bit spanning Tree (ST) adder is used to design CSA. Because Adders are key element in digital design, which are not only performing addition operation, but also many other function such as subtraction, multiplication and division. A Ripple Carry Adder (RCA) gives the most complicated design as-well-as longer computation time so that we may gone for parallel prefix adders. This time critical application we use Spanning tree parallel prefix adder to drive fast results but they lead to increase in area. Proposed Carry Select Adder understands between RCA and BKA in term of area and delay. Delay of Existing adders is larger therefore we have replaced those with Brent Spanning Tree parallel prefix adder which gives fast result. This paper describes comparative performance of 4-bit RCA and 4-Bit BK parallel prefix adders with Our Proposed Spanning Tree adder based carry select adder designed using Xilinx ISE tool.

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