Analysis of Leakage Current Reduction Techniques in SRAM Cell in 90nm CMOS Technology

Scaling of devices in bulk CMOS technology leads to short-channel effects and increase in leakage. Static random access memory (SRAM) is expected to occupy 90% of the area of SoC. Since leakage becomes the major factor in SRAM cell, it is implemented using FinFET. Further, double-gate FinFET devices became a better choice for deep submicron technologies. With this consideration in our research work, 6T SRAM cell is implemented using independent-gate DG FinFET in which both the opposite sides of gates are controlled independently which provides better scalability to the SRAM cell. The device is implemented using different leakage reduction techniques such as gated-Vdd technique and multithreshold voltage technique to reduce leakage. Therefore, power consumption in the SRAM cell is reduced and provides better performance. Independent-gate FinFET SRAM cell using various leakage reduction techniques has been simulated using Cadence virtuoso tool in 45 nm technology.

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Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v8i6.pp4922-4931 ◽

2018 ◽

Vol 8 (6) ◽

pp. 4922

Author(s):

Anil Khatak ◽

Manoj Kumar ◽

Sanjeev Dhull

Keyword(s):

Power Consumption ◽

Leakage Current ◽

Supply Voltage ◽

Cmos Technology ◽

Power Reduction ◽

Total Power ◽

Low Power Consumption ◽

Power Gating ◽

Reduction Techniques ◽

Total Power Consumption

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

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Independent-Double-Gate FINFET SRAM Cell for Drastic Leakage Current Reduction

Lecture Notes in Electrical Engineering - Emerging Technologies and Circuits ◽

10.1007/978-90-481-9379-0_5 ◽

2010 ◽

pp. 67-79 ◽

Cited By ~ 1

Author(s):

Kazuhiko Endo ◽

Shin-ichi O’uchi ◽

Yuki Ishikawa ◽

Yongxun Liu ◽

Takashi Matsukawa ◽

...

Keyword(s):

Leakage Current ◽

Double Gate ◽

Sram Cell ◽

Current Reduction

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Leakage Current Alleviation Techniques for SRAM Cell

International Journal of Engineering and Advanced Technology - Regular Issue ◽

10.35940/ijeat.a1027.1291s52019 ◽

2019 ◽

Vol 9 (1S5) ◽

pp. 112-114

Keyword(s):

Low Power ◽

Random Access ◽

Digital Systems ◽

Handheld Devices ◽

Access Memory ◽

Chip Area ◽

Reduction Techniques ◽

Sram Cell ◽

Current Reduction ◽

Crucial Part

Due to the tremendous increase in the call of handheld devices like mobile, iPods and tablets; certain applications like space and biomedical, it is necessary to have low power consuming digital systems. As a crucial part in digital systems,Static Random Access Memory(SRAM) should consume low power since it occupies about 70% of the total chip area. As the technology is shrinking, SRAM’s leakage power in standby condition is becoming a most critical concern for the low power applications. This paper gives a study of different leakage components present in SRAM and discusses about various current reduction techniques which include Gated VDD, MTCMOS, Dual threshold and Transistor Stacking.

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