scholarly journals Analysis of Leakage Reduction Techniques in Independent-Gate DG FinFET SRAM Cell

2013 ◽  
Vol 2013 ◽  
pp. 1-8
Author(s):  
Vandna Sikarwar ◽  
Saurabh Khandelwal ◽  
Shyam Akashe
Keyword(s):  
Research Work ◽  
Random Access ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Short Channel ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
Sram Cell ◽  
Channel Effects ◽  
Independent Gate

Scaling of devices in bulk CMOS technology leads to short-channel effects and increase in leakage. Static random access memory (SRAM) is expected to occupy 90% of the area of SoC. Since leakage becomes the major factor in SRAM cell, it is implemented using FinFET. Further, double-gate FinFET devices became a better choice for deep submicron technologies. With this consideration in our research work, 6T SRAM cell is implemented using independent-gate DG FinFET in which both the opposite sides of gates are controlled independently which provides better scalability to the SRAM cell. The device is implemented using different leakage reduction techniques such as gated-Vdd technique and multithreshold voltage technique to reduce leakage. Therefore, power consumption in the SRAM cell is reduced and provides better performance. Independent-gate FinFET SRAM cell using various leakage reduction techniques has been simulated using Cadence virtuoso tool in 45 nm technology.

scholarly journals Stacking Techniquefor Low Power Sram

2019 ◽  
Vol 8 (6S2) ◽  
pp. 118-121
Keyword(s):  
Power Systems ◽  
Low Power ◽  
Leakage Current ◽  
Research Work ◽  
Random Access ◽  
Power Reduction ◽  
Access Memory ◽  
Short Channel ◽  
Critical Issues ◽  
Independent Gate

Static random access memory leakage current is becoming one of the critical issues for low-power systems. SRAM-based FinFET Double Gate has become a better option for profound submicron techniques owing to its better short channel effect. In this work, we review some of the leakage current sources and low power reduction technique to reduce leakage. As animprovement of our research work,6T SRAM memory cells can be implemented using independent gate FinFET which gives lower leakage as well as better performance over the shorted gate FinFET mode. This is also implemented using stacking technique to decrease leakage. Therefore, the power devoured by the different SRAM cells is likened with the Tanner tool in 45 nm technique

scholarly journals Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects

2021 ◽  
Author(s):  
Thiago Copetti ◽  
Guilherme Cardoso Medeiros ◽  
Mottaqiallah Taouil ◽  
Said Hamdioui ◽  
Letícia Bolzani Poehls ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Random Access ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Single Event ◽  
Short Channel ◽  
Dynamic Faults ◽  
Sram Cell ◽  
The Impact ◽  
Resistive Defects

AbstractFin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities such as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them, and test escapes may occur. These undetected faults, associated with weak resistive defects, may affect the FinFET-based SRAM reliability during its lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed allowing the evaluation of the ionizing particle’s impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects can positively or negatively influence the cell reliability against SEUs caused by ionizing particles.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

An analytical channel thermal noise model for deep-submicron MOSFETs with short channel effects

2007 ◽  
Vol 51 (7) ◽  
pp. 1034-1038 ◽  
Author(s):  
Jongwook Jeon ◽  
Jong Duk Lee ◽  
Byung-Gook Park ◽  
Hyungcheol Shin
Keyword(s):  
Thermal Noise ◽  
Deep Submicron ◽  
Noise Model ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects

scholarly journals A Comparative Study of 6T and 8T SRAM Cell With Improved Read and Write Margins in 130 nm CMOS Technology

2020 ◽  
Vol 19 ◽  
Keyword(s):  
Comparative Analysis ◽  
Random Access ◽  
Cmos Technology ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Random Access Memories ◽  
Node Voltage ◽  
Improve Stability ◽  
Static Noise ◽  
Better Than

This paper examines the factors that affect the Static Noise Margin (SNM) of a Static Random Access memories which focus on optimizing Read and Write operation of 8T SRAM cell which is better than 6T SRAM cell Using Swing Restoration for Dual Node Voltage. The read and Write time and improve Stability. New 8T SRAM technique on the circuit or architecture level is required. In this paper Comparative Analysis of 6T and 8T SRAM Cells with Improved Read and Write Margin is done for 130 nm Technology with Cadence Virtuoso schematics Tool.

CNTFET-Based Memory Design

2020 ◽  
pp. 16-36
Author(s):  
Shashi Bala ◽  
Mamta Khosla ◽  
Raj Kumar
Keyword(s):  
Random Access ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Suitable Alternative ◽  
Memory Design ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Power ◽  
Effect Transistor

As the feature size of device has been scaling down for many decades, conventional CMOS technology-based static random access memory (SRAM) has reached its limit due to significant leakage power. Therefore, carbon nanotube field effect transistor (CNTFET) can be considered most suitable alternative for SRAM. In this chapter, the performance and stability of CNTFET-based SRAM cells have been analyzed. Numerous figures of merit (FOM) (e.g., read/write noise margin, power dissipation, and read/write delay) have been considered to analyze the performance of CNTFET-based. The static power consumption in CNTFET-based SRAM cell was compared with conventional complementary metal oxide semiconductor (CMOS)-based SRAM cell. Conventional CNTFET and tunnel CNTFET-based SRAMs have also been considered for comparison. From the simulation results, it is observed that tunnel CNTFET SRAM cells have shown improved FOM over conventional CNTFET 6T SRAM cells without losing stability.

Sign in / Sign up

Export Citation Format

Share Document