scholarly journals Mapper and Demapper for LDPC-Coded Systems

2012 ◽  
pp. 104-109
Author(s):  
U. Kiran ◽  
V. Ugendar
Keyword(s):  
Ldpc Codes ◽  
Low Complexity ◽  
Error Correcting Codes ◽  
Modulation Scheme ◽  
Finite Precision ◽  
Decoding Algorithms ◽  
Mapping Strategy ◽  
Coded Systems ◽  
Approximate Expressions ◽  
The Ideal

Low Density Parity Check (LDPC) codes are state-of-art error correcting codes, included in several standards for broadcast transmissions. Iterative softdecision decoding algorithms for LDPC codes reach excellent error correction capability; their performance, however, is strongly affected by finite-precision issues in the representation of inner variables. Great attention has been paid, in recent literature, to the topic of quantization for LDPC decoders, but mostly focusing on binary modulations and analyzing finite precision effects in a disaggregrated manner, i.e., considering separately each block of the receiver. Modern telecommunication standards, instead, often adopt high order modulation schemes, e.g. M-QAM, with the aim to achieve large spectral efficiency. This puts additional quantization problems, that have been poorly debated in previous literature. This paper discusses the choice of suitable quantization characteristics for both the decoder messages and the received samples in LDPC-coded systems using M-QAM schemes. The analysis involves also the demapper block, that provides initial likelihood values for the decoder, by relating its quantization strategy with that of the decoder. A signal label for a signal in a 2m-ary modulation scheme is simply the m-bit pattern assigned to the signal. A mapping strategy refers to the grouping of bits within a codeword, where each mbit group is used to select a 2m-ary signal in accordance with the signal labels. The most obvious mapping strategy is to use each group of m consecutive bits to select a signal. . We will call this the consecutive-bit (CB) mapping strategy. An alternative strategy is the bit-reliability (BR) mapping strategy which will be described below. A new demapper version, based on approximate expressions, is also presented, that introduces a slight deviation from the ideal case but yields a low complexity hardware implementation.

A Min-Sum Algorithm Suitable for Hardware Implementation Based on LDPC Codes

2011 ◽  
Vol 271-273 ◽  
pp. 458-463
Author(s):  
Rui Ping Chen ◽  
Zhong Xun Wang ◽  
Xin Qiao Yu
Keyword(s):  
Hardware Implementation ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Scaling Factor ◽  
Computation Complexity ◽  
Decoding Complexity ◽  
Decoding Algorithms ◽  
Hardware Resource ◽  
Simulation Results ◽  
Ber Performance

Decoding algorithms with strong practical value not only have good decoding performance, but also have the computation complexity as low as possible. For this purpose, the paper points out the modified min-sum decoding algorithm(M-MSA). On the condition of no increasing in the decoding complexity, it makes the error-correcting performance improved by adding the appropriate scaling factor based on the min-sum algorithm(MSA), and it is very suitable for hardware implementation. Simulation results show that this algorithm has good BER performance, low complexity and low hardware resource utilization, and it would be well applied in the future.

Hybrid Decoding Algorithm for LDPC Codes with Circles

2011 ◽  
Vol 271-273 ◽  
pp. 258-263
Author(s):  
Li Shuang Hu ◽  
Ming Shan Liu ◽  
Yuan Zhou ◽  
Yang Sun
Keyword(s):  
Error Rate ◽  
Belief Propagation ◽  
Additive White Gaussian Noise ◽  
Ldpc Codes ◽  
Error Correcting Codes ◽  
Parity Check ◽  
Likelihood Ratios ◽  
Decoding Algorithms ◽  
Variable Node ◽  
Check Node

At present, Low-Density Parity-Check (LDPC) codes widely used in many fields of communications have the best performance of all the Error Correcting Codes (ECC). This paper mainly studies the decoding algorithms of LDPC. It proposes an improved algorithm which is named Check-Variable nodes Hybrid(CVH) algorithm on the basis of the existing algorithms. The CVH algorithm can reduce the computational complexity during the check-node update while overcome with the correlation between the variable-node news in a code with circles. As well as, comparing with the original algorithms the performance of the new one saves 0.1 and 0.3 dB than Log-likelihood Ratios (LLR) Belief Propagation (BP) and BP - based algorithms under Additive White Gaussian Noise (AWGN) channel when the Bit Error Rate (BER) falls to through the simulation. This point shows that this algorithm can increase the decoding performance and reduce the error rate effectively.

Bit-Reliability Based Low-Complexity Decoding Algorithms for Non-Binary LDPC Codes

2014 ◽  
Vol 62 (12) ◽  
pp. 4230-4240 ◽  
Author(s):  
Qin Huang ◽  
Mu Zhang ◽  
Zulin Wang ◽  
Lu Wang
Keyword(s):  
Ldpc Codes ◽  
Low Complexity ◽  
Decoding Algorithms

scholarly journals Low Complexity Iterative Rake Decision Feedback Equalizer for Zero-Padded OTFS systems

2020 ◽  
Author(s):  
Tharaj Thaj ◽  
Emanuele Viterbo
Keyword(s):  
Orthogonal Frequency Division Multiplexing ◽  
Minimum Mean Square Error ◽  
Low Complexity ◽  
Error Correcting Codes ◽  
Decision Feedback ◽  
Maximal Ratio Combining ◽  
Modulation Scheme ◽  
Decision Feedback Equalizer ◽  
Input Output ◽  
Time Frequency

<div>This paper presents a linear complexity iterative rake detector for the recently proposed orthogonal time frequency space (OTFS) modulation scheme. The basic idea is to extract and coherently combine the received multipath components of the transmitted symbols in the delay-Doppler grid using maximal ratio combining (MRC) to improve the SNR of the combined signal. We reformulate the OTFS input-output relation in simple vector form by placing guard null symbols or zero padding (ZP) in the delay-Doppler grid and exploiting the resulting circulant property of the blocks of the channel matrix. Using this vector input-output relation we propose a low complexity iterative decision feedback equalizer (DFE) based on MRC. The performance and complexity of the proposed detector favorably compares with the state of the art message passing detector. An alternative time domain MRC based detector is also proposed for even faster detection. We further propose a Gauss-Seidel based over-relaxation parameter in the rake detector to improve the performance and the convergence speed of the iterative detection. We also show how the MRC detector can be combined with outer error-correcting codes to operate as a turbo DFE scheme to further improve the error performance. </div><div>All results are compared with a baseline orthogonal frequency division multiplexing (OFDM) scheme employing a single tap minimum mean square error (MMSE) equalizer.</div>

scholarly journals Design and Analysis of Adaptive Message Coding on LDPC Decoder with Faulty Storage

2018 ◽  
Vol 2018 ◽  
pp. 1-13
Author(s):  
Guangjun Ge ◽  
Liuguo Yin
Keyword(s):  
Low Complexity ◽  
Theoretic Analysis ◽  
Finite Precision ◽  
Ldpc Decoder ◽  
Decoding Algorithms ◽  
Performance Loss ◽  
Coding Scheme ◽  
Evolution Analysis ◽  
Modular Redundancy ◽  
Residual Errors

Unreliable message storage severely degrades the performance of LDPC decoders. This paper discusses the impacts of message errors on LDPC decoders and schemes improving the robustness. Firstly, we develop a discrete density evolution analysis for faulty LDPC decoders, which indicates that protecting the sign bits of messages is effective enough for finite-precision LDPC decoders. Secondly, we analyze the effects of quantization precision loss for static sign bit protection and propose an embedded dynamic coding scheme by adaptively employing the least significant bits (LSBs) to protect the sign bits. Thirdly, we give a construction of Hamming product code for the adaptive coding and present low complexity decoding algorithms. Theoretic analysis indicates that the proposed scheme outperforms traditional triple modular redundancy (TMR) scheme in decoding both threshold and residual errors, while Monte Carlo simulations show that the performance loss is less than 0.2 dB when the storage error probability varies from 10-3 to 10-4.

scholarly journals Low Complexity Iterative Rake Decision Feedback Equalizer for Zero-Padded OTFS systems

2021 ◽  
Author(s):  
Tharaj Thaj ◽  
Emanuele Viterbo
Keyword(s):  
Orthogonal Frequency Division Multiplexing ◽  
Minimum Mean Square Error ◽  
Low Complexity ◽  
Error Correcting Codes ◽  
Decision Feedback ◽  
Maximal Ratio Combining ◽  
Modulation Scheme ◽  
Decision Feedback Equalizer ◽  
Input Output ◽  
Time Frequency

<div>This paper presents a linear complexity iterative rake detector for the recently proposed orthogonal time frequency space (OTFS) modulation scheme. The basic idea is to extract and coherently combine the received multipath components of the transmitted symbols in the delay-Doppler grid using maximal ratio combining (MRC) to improve the SNR of the combined signal. We reformulate the OTFS input-output relation in simple vector form by placing guard null symbols or zero padding (ZP) in the delay-Doppler grid and exploiting the resulting circulant property of the blocks of the channel matrix. Using this vector input-output relation we propose a low complexity iterative decision feedback equalizer (DFE) based on MRC. The performance and complexity of the proposed detector favorably compares with the state of the art message passing detector. An alternative time domain MRC based detector is also proposed for even faster detection. We further propose a Gauss-Seidel based over-relaxation parameter in the rake detector to improve the performance and the convergence speed of the iterative detection. We also show how the MRC detector can be combined with outer error-correcting codes to operate as a turbo DFE scheme to further improve the error performance. </div><div>All results are compared with a baseline orthogonal frequency division multiplexing (OFDM) scheme employing a single tap minimum mean square error (MMSE) equalizer.</div>

scholarly journals Weighted-Bit-Flipping-Based Sequential Scheduling Decoding Algorithms for LDPC Codes

2013 ◽  
Vol 2013 ◽  
pp. 1-6
Author(s):  
Qing Zhu ◽  
Le-nan Wu
Keyword(s):  
Belief Propagation ◽  
Scheduling Algorithm ◽  
Simple Algorithm ◽  
Ldpc Codes ◽  
Satellite Communications ◽  
Low Complexity ◽  
Computation Complexity ◽  
Tanner Graph ◽  
Decoding Algorithms ◽  
Video Broadcasting

Low-density parity-check (LDPC) codes can be applied in a lot of different scenarios such as video broadcasting and satellite communications. LDPC codes are commonly decoded by an iterative algorithm called belief propagation (BP) over the corresponding Tanner graph. The original BP updates all the variable-nodes simultaneously, followed by all the check-nodes simultaneously as well. We propose a sequential scheduling algorithm based on weighted bit-flipping (WBF) algorithm for the sake of improving the convergence speed. Notoriously, WBF is a low-complexity and simple algorithm. We combine it with BP to obtain advantages of these two algorithms. Flipping function used in WBF is borrowed to determine the priority of scheduling. Simulation results show that it can provide a good tradeoff between FER performance and computation complexity for short-length LDPC codes.

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