scholarly journals Low Complexity Bit Reliability and Predication Based Symbol Value Selection Decoding Algorithms for Non-Binary LDPC Codes

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 142691-142703
Author(s):  
Waheed Ullah ◽  
Ling Cheng ◽  
Fambirai Takawira
Keyword(s):  
Ldpc Codes ◽  
Low Complexity ◽  
Decoding Algorithms

A Min-Sum Algorithm Suitable for Hardware Implementation Based on LDPC Codes

2011 ◽  
Vol 271-273 ◽  
pp. 458-463
Author(s):  
Rui Ping Chen ◽  
Zhong Xun Wang ◽  
Xin Qiao Yu
Keyword(s):  
Hardware Implementation ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Scaling Factor ◽  
Computation Complexity ◽  
Decoding Complexity ◽  
Decoding Algorithms ◽  
Hardware Resource ◽  
Simulation Results ◽  
Ber Performance

Decoding algorithms with strong practical value not only have good decoding performance, but also have the computation complexity as low as possible. For this purpose, the paper points out the modified min-sum decoding algorithm(M-MSA). On the condition of no increasing in the decoding complexity, it makes the error-correcting performance improved by adding the appropriate scaling factor based on the min-sum algorithm(MSA), and it is very suitable for hardware implementation. Simulation results show that this algorithm has good BER performance, low complexity and low hardware resource utilization, and it would be well applied in the future.

Bit-Reliability Based Low-Complexity Decoding Algorithms for Non-Binary LDPC Codes

2014 ◽  
Vol 62 (12) ◽  
pp. 4230-4240 ◽  
Author(s):  
Qin Huang ◽  
Mu Zhang ◽  
Zulin Wang ◽  
Lu Wang
Keyword(s):  
Ldpc Codes ◽  
Low Complexity ◽  
Decoding Algorithms

scholarly journals Mapper and Demapper for LDPC-Coded Systems

2012 ◽  
pp. 104-109
Author(s):  
U. Kiran ◽  
V. Ugendar
Keyword(s):  
Ldpc Codes ◽  
Low Complexity ◽  
Error Correcting Codes ◽  
Modulation Scheme ◽  
Finite Precision ◽  
Decoding Algorithms ◽  
Mapping Strategy ◽  
Coded Systems ◽  
Approximate Expressions ◽  
The Ideal

Low Density Parity Check (LDPC) codes are state-of-art error correcting codes, included in several standards for broadcast transmissions. Iterative softdecision decoding algorithms for LDPC codes reach excellent error correction capability; their performance, however, is strongly affected by finite-precision issues in the representation of inner variables. Great attention has been paid, in recent literature, to the topic of quantization for LDPC decoders, but mostly focusing on binary modulations and analyzing finite precision effects in a disaggregrated manner, i.e., considering separately each block of the receiver. Modern telecommunication standards, instead, often adopt high order modulation schemes, e.g. M-QAM, with the aim to achieve large spectral efficiency. This puts additional quantization problems, that have been poorly debated in previous literature. This paper discusses the choice of suitable quantization characteristics for both the decoder messages and the received samples in LDPC-coded systems using M-QAM schemes. The analysis involves also the demapper block, that provides initial likelihood values for the decoder, by relating its quantization strategy with that of the decoder. A signal label for a signal in a 2m-ary modulation scheme is simply the m-bit pattern assigned to the signal. A mapping strategy refers to the grouping of bits within a codeword, where each mbit group is used to select a 2m-ary signal in accordance with the signal labels. The most obvious mapping strategy is to use each group of m consecutive bits to select a signal. . We will call this the consecutive-bit (CB) mapping strategy. An alternative strategy is the bit-reliability (BR) mapping strategy which will be described below. A new demapper version, based on approximate expressions, is also presented, that introduces a slight deviation from the ideal case but yields a low complexity hardware implementation.

scholarly journals Weighted-Bit-Flipping-Based Sequential Scheduling Decoding Algorithms for LDPC Codes

2013 ◽  
Vol 2013 ◽  
pp. 1-6
Author(s):  
Qing Zhu ◽  
Le-nan Wu
Keyword(s):  
Belief Propagation ◽  
Scheduling Algorithm ◽  
Simple Algorithm ◽  
Ldpc Codes ◽  
Satellite Communications ◽  
Low Complexity ◽  
Computation Complexity ◽  
Tanner Graph ◽  
Decoding Algorithms ◽  
Video Broadcasting

Low-density parity-check (LDPC) codes can be applied in a lot of different scenarios such as video broadcasting and satellite communications. LDPC codes are commonly decoded by an iterative algorithm called belief propagation (BP) over the corresponding Tanner graph. The original BP updates all the variable-nodes simultaneously, followed by all the check-nodes simultaneously as well. We propose a sequential scheduling algorithm based on weighted bit-flipping (WBF) algorithm for the sake of improving the convergence speed. Notoriously, WBF is a low-complexity and simple algorithm. We combine it with BP to obtain advantages of these two algorithms. Flipping function used in WBF is borrowed to determine the priority of scheduling. Simulation results show that it can provide a good tradeoff between FER performance and computation complexity for short-length LDPC codes.

scholarly journals Error Exponents of LDPC Codes under Low-Complexity Decoding

Entropy ◽  
2021 ◽  
Vol 23 (2) ◽  
pp. 253
Author(s):  
Pavel Rybin ◽  
Kirill Andreev ◽  
Victor Zyablov
Keyword(s):  
Linear Codes ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Parity Check ◽  
Error Exponent ◽  
Error Exponents ◽  
Decoding Algorithms ◽  
Symmetric Channel ◽  
Low Density Parity Check ◽  
Specific Construction

This paper deals with the specific construction of binary low-density parity-check (LDPC) codes. We derive lower bounds on the error exponents for these codes transmitted over the memoryless binary symmetric channel (BSC) for both the well-known maximum-likelihood (ML) and proposed low-complexity decoding algorithms. We prove the existence of such LDPC codes that the probability of erroneous decoding decreases exponentially with the growth of the code length while keeping coding rates below the corresponding channel capacity. We also show that an obtained error exponent lower bound under ML decoding almost coincide with the error exponents of good linear codes.

scholarly journals High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 700
Author(s):  
Yufei Zhu ◽  
Zuocheng Xing ◽  
Zerun Li ◽  
Yang Zhang ◽  
Yifan Hu
Keyword(s):  
High Performance ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Cmos Technology ◽  
Area Efficiency ◽  
Prior Art ◽  
New Radio ◽  
High Area ◽  
Significant Area ◽  
Area Efficient

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

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