scholarly journals Design and Analysis of Adaptive Message Coding on LDPC Decoder with Faulty Storage

2018 ◽  
Vol 2018 ◽  
pp. 1-13
Author(s):  
Guangjun Ge ◽  
Liuguo Yin
Keyword(s):  
Low Complexity ◽  
Theoretic Analysis ◽  
Finite Precision ◽  
Ldpc Decoder ◽  
Decoding Algorithms ◽  
Performance Loss ◽  
Coding Scheme ◽  
Evolution Analysis ◽  
Modular Redundancy ◽  
Residual Errors

Unreliable message storage severely degrades the performance of LDPC decoders. This paper discusses the impacts of message errors on LDPC decoders and schemes improving the robustness. Firstly, we develop a discrete density evolution analysis for faulty LDPC decoders, which indicates that protecting the sign bits of messages is effective enough for finite-precision LDPC decoders. Secondly, we analyze the effects of quantization precision loss for static sign bit protection and propose an embedded dynamic coding scheme by adaptively employing the least significant bits (LSBs) to protect the sign bits. Thirdly, we give a construction of Hamming product code for the adaptive coding and present low complexity decoding algorithms. Theoretic analysis indicates that the proposed scheme outperforms traditional triple modular redundancy (TMR) scheme in decoding both threshold and residual errors, while Monte Carlo simulations show that the performance loss is less than 0.2 dB when the storage error probability varies from 10-3 to 10-4.

scholarly journals Mapper and Demapper for LDPC-Coded Systems

2012 ◽  
pp. 104-109
Author(s):  
U. Kiran ◽  
V. Ugendar
Keyword(s):  
Ldpc Codes ◽  
Low Complexity ◽  
Error Correcting Codes ◽  
Modulation Scheme ◽  
Finite Precision ◽  
Decoding Algorithms ◽  
Mapping Strategy ◽  
Coded Systems ◽  
Approximate Expressions ◽  
The Ideal

Low Density Parity Check (LDPC) codes are state-of-art error correcting codes, included in several standards for broadcast transmissions. Iterative softdecision decoding algorithms for LDPC codes reach excellent error correction capability; their performance, however, is strongly affected by finite-precision issues in the representation of inner variables. Great attention has been paid, in recent literature, to the topic of quantization for LDPC decoders, but mostly focusing on binary modulations and analyzing finite precision effects in a disaggregrated manner, i.e., considering separately each block of the receiver. Modern telecommunication standards, instead, often adopt high order modulation schemes, e.g. M-QAM, with the aim to achieve large spectral efficiency. This puts additional quantization problems, that have been poorly debated in previous literature. This paper discusses the choice of suitable quantization characteristics for both the decoder messages and the received samples in LDPC-coded systems using M-QAM schemes. The analysis involves also the demapper block, that provides initial likelihood values for the decoder, by relating its quantization strategy with that of the decoder. A signal label for a signal in a 2m-ary modulation scheme is simply the m-bit pattern assigned to the signal. A mapping strategy refers to the grouping of bits within a codeword, where each mbit group is used to select a 2m-ary signal in accordance with the signal labels. The most obvious mapping strategy is to use each group of m consecutive bits to select a signal. . We will call this the consecutive-bit (CB) mapping strategy. An alternative strategy is the bit-reliability (BR) mapping strategy which will be described below. A new demapper version, based on approximate expressions, is also presented, that introduces a slight deviation from the ideal case but yields a low complexity hardware implementation.

Low Complexity Generalized-LDPC Decoder Based on Trellis Splicing

2020 ◽  
pp. 1-1
Author(s):  
Xuan Zhou ◽  
Zheng Ma ◽  
Li Li ◽  
Ming Xiao
Keyword(s):  
Low Complexity ◽  
Ldpc Decoder

scholarly journals Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 516
Author(s):  
Tram Thi Bao Nguyen ◽  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Wireless Communication ◽  
High Throughput ◽  
Low Complexity ◽  
Ldpc Decoder ◽  
Processor Architectures ◽  
New Radio ◽  
Decoder Architecture ◽  
Check Node ◽  
Information Update ◽  
Wireless Standards

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

Low-Complexity Intra-Coding Scheme for HEVC

2016 ◽  
Vol 35 (12) ◽  
pp. 4331-4349 ◽  
Author(s):  
Xiwu Shang ◽  
Guozhong Wang ◽  
Tao Fan ◽  
Yan Li ◽  
Yifan Zuo
Keyword(s):  
Low Complexity ◽  
Intra Coding ◽  
Coding Scheme

“Soft Error” Correction Method Based on Low Complexity Coding and Encoding Algorithm

2014 ◽  
Vol 556-562 ◽  
pp. 6344-6349
Author(s):  
Yan Kang Wei ◽  
Da Ming Wang ◽  
Wei Jia Cui
Keyword(s):  
Fault Tolerance ◽  
Error Correction ◽  
Fault Tolerant ◽  
Low Complexity ◽  
Correction Method ◽  
Block Codes ◽  
Decoding Algorithms ◽  
Linear Block Codes ◽  
Data Errors ◽  
Linear Block

SEU is one of the major challenges affecting the reliability of computers on-board. In this paper, we design a kind of encoding and decoding algorithms with a low complexity based on the data correction method to resolve the data stream errors SEU may bring. Firstly, we use the theory of linear block codes to analyze various methods of data fault tolerance, and then from the encoding and decoding principle of linear block codes we design a kind of encoding and decoding algorithms with a low complexity of linear block code, The fault-tolerant coding method can effectively correct single-bit data errors caused by SEU, with low fault-tolerant overhead. Fault injection experiments show that: this method can effectively correct data errors caused by single event upset. Compared with other common error detection or correction methods, error correction performance of this method is superior, while its fault tolerance cost is less.

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