scholarly journals A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture

2012 ◽  
Vol 12 (4) ◽  
pp. 19-24 ◽  
Author(s):  
J. WANG ◽  
Y. LI ◽  
H. LI
Keyword(s):  
Network On Chip ◽  
Input Buffer ◽  
Analytical Strategy ◽  
On Chip ◽  
A Performance

An analytical model for Network-on-Chip with finite input buffer

2010 ◽  
Vol 5 (1) ◽  
pp. 126-134 ◽  
Author(s):  
Jian Wang ◽  
Yu-bai Li ◽  
Chang Wu
Keyword(s):  
Analytical Model ◽  
Network On Chip ◽  
Input Buffer ◽  
On Chip

scholarly journals A Performance Enhanced Dual-switch Network-on-chip Architecture

2015 ◽  
Vol 8 (0) ◽  
pp. 85-94 ◽  
Author(s):  
Lian Zeng ◽  
Xin Jiang ◽  
Takahiro Watanabe
Keyword(s):  
Network On Chip ◽  
On Chip ◽  
A Performance

Design and implementation of a network on chip-based simulator: a performance study

2014 ◽  
Vol 9 (1/2) ◽  
pp. 95 ◽  
Author(s):  
V. Sanju ◽  
C. Koushika ◽  
R. Sharmili ◽  
Niranjan Chiplunkar ◽  
M. Khalid
Keyword(s):  
Network On Chip ◽  
Performance Study ◽  
Design And Implementation ◽  
On Chip ◽  
A Performance
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