scholarly journals Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

2013 ◽  
Vol 04 (03) ◽  
pp. 276-279
Author(s):  
Omnia S. Ahmed ◽  
Mohamed F. Abu-Elyazeed ◽  
Mohamed B. Abdelhalim ◽  
Hassanein H. Amer ◽  
Ahmed H. Madian
Keyword(s):  
Power Estimation ◽  
Cmos Circuits ◽  
Gate Delay ◽  
Delay Model ◽  
Dynamic Power

scholarly journals Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model

2016 ◽  
Vol 7 (1) ◽  
pp. 89-94 ◽  
Author(s):  
Omnia S. Fadl ◽  
Mohamed F. Abu-Elyazeed ◽  
Mohamed B. Abdelhalim ◽  
Hassanein H. Amer ◽  
Ahmed H. Madian
Keyword(s):  
Power Estimation ◽  
Logic Circuits ◽  
Gate Delay ◽  
Combinational Logic ◽  
Delay Model ◽  
Dynamic Power ◽  
Combinational Logic Circuits

scholarly journals A gate-delay model for high-speed CMOS circuits

1994 ◽  
Author(s):  
Florentin Dartu ◽  
Noel Menezes ◽  
Jessica Qian ◽  
Lawrence T. Pillage
Keyword(s):  
High Speed ◽  
Cmos Circuits ◽  
Gate Delay ◽  
Delay Model

Quantifying Error in Dynamic Power Estimation of CMOS Circuits

2005 ◽  
Vol 42 (3) ◽  
pp. 253-264 ◽  
Author(s):  
Puneet Gupta ◽  
Andrew B. Kahng ◽  
Swamy Muddu
Keyword(s):  
Power Estimation ◽  
Cmos Circuits ◽  
Dynamic Power
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