A gate-delay model for high-speed CMOS circuits

32nd Design Automation Conference ◽

10.1145/196244.196562 ◽

1994 ◽

Cited By ~ 64

Author(s):

Florentin Dartu ◽

Noel Menezes ◽

Jessica Qian ◽

Lawrence T. Pillage

Keyword(s):

High Speed ◽

Cmos Circuits ◽

Gate Delay ◽

Delay Model

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An accurate gate delay model for high speed digital and analog circuits

2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software ◽

10.1109/dcas.2008.4695915 ◽

2008 ◽

Cited By ~ 1

Author(s):

Josef Dobes ◽

Vaclav Panko ◽

Ladislav Pospisil

Keyword(s):

Analog Circuits ◽

High Speed ◽

Gate Delay ◽

Delay Model

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Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

Circuits and Systems ◽

10.4236/cs.2013.43037 ◽

2013 ◽

Vol 04 (03) ◽

pp. 276-279

Author(s):

Omnia S. Ahmed ◽

Mohamed F. Abu-Elyazeed ◽

Mohamed B. Abdelhalim ◽

Hassanein H. Amer ◽

Ahmed H. Madian

Keyword(s):

Power Estimation ◽

Cmos Circuits ◽

Gate Delay ◽

Delay Model ◽

Dynamic Power

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A gate delay model considering temporal proximity of Multiple Input Switching

2009 International SoC Design Conference (ISOCC) ◽

10.1109/socdc.2009.5423815 ◽

2009 ◽

Cited By ~ 1

Author(s):

Janghyuk Shin ◽

Juho Kim ◽

Naeun Jang ◽

Eunsuk Park ◽

Yangmin Choi

Keyword(s):

Gate Delay ◽

Delay Model ◽

Temporal Proximity ◽

Multiple Input ◽

Multiple Input Switching

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Amplification, feedback, and sub-biasing: Applying analog techniques to high-speed, low-power digital CMOS circuits

2017 International Symposium on Signals, Circuits and Systems (ISSCS) ◽

10.1109/isscs.2017.8034947 ◽

2017 ◽

Author(s):

Daniel Foty

Keyword(s):

Low Power ◽

High Speed ◽

Cmos Circuits ◽

Digital Cmos

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Design of Gate Delay and Gate Interval Time for Four-Quadrant Gate System at Railroad-Highway Grade Crossings

Transportation Research Record Journal of the Transportation Research Board ◽

10.1177/0361198196155300118 ◽

1996 ◽

Vol 1553 (1) ◽

pp. 124-131 ◽

Cited By ~ 3

Author(s):

Fred Coleman ◽

oung J. Moon

Keyword(s):

High Speed ◽

Signalized Intersections ◽

Design Approach ◽

Gate Delay ◽

High Speed Rail ◽

Interval Time ◽

Signal Change ◽

Gate System ◽

Grade Crossings ◽

Four Quadrant

A design methodology for gate delay and gate interval time for at-grade crossings using four-quadrant gates is developed. The design approach is based on the concept of dilemma zones related to signal change intervals at signalized intersections. The design approach is validated based on data from six sites in Illinois on a proposed high-speed rail corridor. Gate delay and gate interval times are determined that provide an optimal safe decision point to allow a driver to stop before the crossing or to proceed through the crossing without becoming trapped by the exit gates.

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