Quality Monitors and Inspection Criteria for Bare Die Flip Chip Ball Grid Array and Bare Die PoP Packages.

2014 ◽  
Vol 2014 (1) ◽  
pp. 000533-000536
Author(s):  
Kiran Vanam ◽  
Anthony Newman ◽  
Mori Poustinchi ◽  
Stephen Stewart
Keyword(s):  
Form Factor ◽  
High Temperature ◽  
Flip Chip ◽  
Lower Cost ◽  
Smart Phone ◽  
Ball Grid Array ◽  
Heat Spreader ◽  
Fine Line ◽  
Key Drivers ◽  
Test Operations

Package form factor and cost are one of the key drivers in smart phone and tablet landscape. In order to meet these requirements hand held market has seen emergence of bare die flip chip ball grid array (BD FCBGA) and bare die package on package (BD PoP). As the name implies, these packages don't have a mold cap or heat spreader surrounding the silicon die resulting in lower cost and smaller form factor. Further package thickness reduction is possible by thinning of silicon die without significantly affecting high temperature (HT) warpage or coplanarity. One of the main concerns with aforementioned bare die package (BDP) configurations is die crack failure during assembly, testing, shipping or surface mount operation (SMT). The propensity of die crack failures further increases as thinner die is employed to meet overall package height requirements. This work focusses on evaluating various inspection tools for detecting gross die cracks to fine line cracks up to ~ 0.7 μm wide. Some of the key considerations for inspection tools, at assembly and test operations will be presented.

Fine line panel level fan out changes the SiP landscape

2018 ◽  
Vol 2018 (1) ◽  
pp. 000349-000354
Author(s):  
David Fang ◽  
Michael Hsu ◽  
CC Chang ◽  
KW Chung ◽  
Alex Liu ◽  
...  
Keyword(s):  
Production Efficiency ◽  
Flip Chip ◽  
Lower Cost ◽  
Transmission Loss ◽  
New Technology ◽  
Moore’S Law ◽  
Moore's Law ◽  
Fine Line ◽  
To Come ◽  
Application Requirements

Abstract Moore's Law has been through many challenges in the last few years. The transistors continued to shrink to smaller sizes but the benefit of better performance and lower cost that comes along with shrinking is facing difficulties. Semiconductor industries are trying to come up with new ways to keep the Moore's Law going on two different fronts: where foundries are working on more Moore solutions and packaging houses are working on more than Moore solutions. Recently the industry has been considering the chip splitting and re-constitution in the form of SiP which has relatively shorter development time and lower cost than the SoC. But traditional SiP with wirebonding or FC connections to substrate will lead to high transmission loss and power consumption. A new fine line SiP solution is required to shorten the connection between chips to improve the performance. Different from the 3DIC and 2.5DIC technologies, fine line panel level fan out has the advantages of good performance, design flexibility, and high production efficiency. This paper will discuss about the challenges in setting up this technology including establishing standards, tools preparation, and process difficulties. The dedicated machines that handle the fine line panel level fan out are critical. It is not easy to select suitable tools for this new technology. We also need to co-develop with tool vendors for some process stages which suitable tools from existing industries could not be easily found. Additionally, panel warpage and chip shift are two of major process challenges. Experiences on overcoming these difficulties will be shared. Different structures and processes have been developed for varied application requirements. The chip first approach encapsulates chips and then build RDL layers on the encapsulation surface. It is suitable for mobile AP, baseband, ASIC, PMIC, and memory. The chip last solution build RDL first, then flip chip mounting the bumped chips on the RDL. The RDL can be tested before the mounting of chips. It is suitable for CPU, GPU, FPGA, and thermal sensitive devices. Pillars in fan out is a chip middle solution. It uses Cu pillars to connect top and bottom RDLs which is good for chip stacking. Currently the 5/5um line/space is already been qualified. 3/3um under development and tool capability is 2/2um. Several real cases will be demonstrated in this paper to help the readers understand this technology. This technology is expected to be crucial for the coming era of 5G, automotive, IoT, and AI. It is believed that this technology can be applied to different kinds of end applications. For example, multi-chip stacking in a fan out package to achieve high bandwidth performance. Fan out stacking of logic and memory chips which can replace the existing PoP. Using fan out to integrate passives and/or other chips can achieve a compact SiP. Fan out could be one of the embedded substrate. Fan out RDL process can also be a suitable platform for antenna in package designs. This paper will introduce the challenges of Moore's law as beginning, and then explain the advantages and the challenges of fine line panel fan out technology, and the proposed approaches to address those challenges.

An Evaluation of Thermal Enhancements to Flip-Chip-Plastic Ball Grid Array (FC-PBGA) Packages

2003 ◽  
Author(s):  
K. Ramakrishna ◽  
T.-Y. Tom Lee
Keyword(s):  
Thermal Conductivity ◽  
Thermal Resistance ◽  
Thermal Performance ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Heat Spreader ◽  
Thermal Enhancement ◽  
Plastic Ball ◽  
Plastic Ball Grid Array ◽  
Underfill Material

Flip-chip plastic ball grid array (FC-PBGA) packages are fast becoming the industry norm, in particular in the performance and cost driven consumer electronics sector. Since high thermal conductivity (k∼15–20 W/(m K)) ceramic substrate is replaced by a low conductivity (k∼0.2–0.5 W/(m K)) organic substrate in the FC-PBGA packages, enhancement of thermal performance of these packages to meet ever increasing demands is crucial for their wide spread use. In this study, enhancements to thermal performance of FC-PBGA packages due to material and design changes and external means such as heat spreaders and overmolding of the packages have been evaluated by solving a conjugate heat transfer models using the methods of computational fluid dynamic. The thermal enhancements evaluated in this study include the effect of thermal conductivity of the chip to package interconnect due to change in underfill material and the C4 bump pitch, effect of package to printed wiring board (PWB) interconnection through the use of thermal balls, effect of a heat spreader on the backside of the die, and overmolding the die without and with a heat spreader. Thermal performance of the FC-PBGA packages have been studied using junction to ambient thermal resistance, Θja, junction-to-board thermal resistance Ψjb, and junction to case thermal resistance ΨjT under natural and forced convection for freestream velocities up to 2 m/s and the for following ranges of parameters: Substrate size: 25 to 35 mm, die size: 6.19×7.81 mm (48 mm2 area) and 9.13×12.95 mm (118 mm2 area), C4 pitch: 250 mm, 150 mm and below, underfill material thermal conductivity: 0.6 to 3.0 W/(m K), no thermal balls between the package and the PWB to 9×9 array of thermal balls on 1.27 mm square pitch, and with copper heat spreader on the back of the bare and overmolded die. Based on previous experience, predictions in this study are expected to be within ±10% of measured data. The following conclusions are drawn from this study: 1. It is concluded that the thermal conductivity of the underfill materials in the range 0.6 to 10 W/(m K) is negligible. 2. It is also concluded that the bump pitch can decrease thermal resistances by 12 to 15 %. The change may be smaller with large die area. 3. Thermal balls (C5) connected to the PTHs in the PWB can decrease thermal resistance by about 10% to 15% as the number of thermal balls & PTHs increase zero to 9×9 on 1.27 mm pitch. The effect die size on this thermal enhancement is more noticeable on Ψjb. 4. Heat spreader on the back of the die decreases Θja by a small amount (6–7%) in natural convection and a large amount, about 25% in forced convection. 5. Overmolded die with heat spreader on the top of the overmold provides better thermal enhancement than heat spreader alone up to about 1 m/s. Beyond 1 m/s, heat spreader (without overmold) performs slightly better.

Super-Conducting Quantum Interference Device Technique: 3-D Localization of a Short within a Flip Chip Assembly

2001 ◽  
Author(s):  
Kendall Scott Wills ◽  
Omar Diaz de Leon ◽  
Kartik Ramanujachar ◽  
Charles P. Todd
Keyword(s):  
Form Factor ◽  
Failure Analysis ◽  
Time Domain ◽  
Quantum Interference ◽  
Flip Chip ◽  
Time Domain Reflectometry ◽  
Interfacial Region ◽  
Precise Localization ◽  
Super Conducting ◽  
Accuracy Of Measurement

Abstract In the current generations of devices the die and its package are closely integrated to achieve desired performance and form factor. As a result, localization of continuity failures to either the die or the package is a challenging step in failure analysis of such devices. Time Domain Reflectometry [1] (TDR) is used to localize continuity failures. However the accuracy of measurement with TDR is inadequate for effective localization of the failsite. Additionally, this technique does not provide direct 3-Dimenstional information about the location of the defect. Super-conducting Quantum Interference Device (SQUID) Microscope is useful in localizing shorts in packages [2]. SQUID microscope can localize defects to within 5um in the X and Y directions and 35um in the Z direction. This accuracy is valuable in precise localization of the failsite within the die, package or the interfacial region in flipchip assemblies.

The Study of Underfill Epoxy Hardness in Reducing Curing Process Time for Flip Chip Packaging

2011 ◽  
Vol 462-463 ◽  
pp. 1194-1199
Author(s):  
Zainudin Kornain ◽  
Azman Jalar ◽  
Rozaidi Rashid ◽  
Shahrum Abdullah
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Process Time ◽  
Curing Process ◽  
Curing Time ◽  
Hold Temperature ◽  
Flip Chip Packaging ◽  
Time Cycle ◽  
The Impact

Underfilling is the vital process to reduce the impact of the thermal stress that results from the mismatch in the co-efficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. This paper reported the pattern of underfill’s hardness during curing process for large die Ceramic Flip Chip Ball Grid Array (FC-CBGA). A commercial amine based underfill epoxy was dispensed into HiCTE FC-CBGA and cured in curing oven under a new method of two-step curing profile. Nano-identation test was employed to investigate the hardness of underfill epoxy during curing steps. The result has shown the almost similar hardness of fillet area and centre of the package after cured which presented uniformity of curing states. The total curing time/cycle in production was potentially reduced due to no significant different of hardness after 60 min and 120 min during the period of second hold temperature.

scholarly journals FCCSP IMC growth under reliability stress follows automotive criteria

2019 ◽  
Vol 3 (1) ◽  
pp. 70-83
Author(s):  
Wei Wei Liu ◽  
Berdy Weng ◽  
Scott Chen
Keyword(s):  
High Temperature ◽  
Flip Chip ◽  
Stress Test ◽  
Temperature Cycling ◽  
Content Type ◽  
Initial Stage ◽  
High Temperature Storage ◽  
Temperature Cycling Test ◽  
Temperature Storage

Purpose The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu3Sn layer which locate between the intermetallic Cu6Sn5 and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu3Sn and Cu6Sn5 do affected seriously by heat, but Ni3Sn4 is not affected by heat or moisture. Design/methodology/approach The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology. Findings The Cu6Sn5 intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 µm at high temperature storage 2,000 h testing, and the second is Cu3Sn IMC. Cu6Sn5 IMC will convert to Cu3Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu3Sn IMC, which has quality concerning issue if the void’s density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni3Sn4 IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni3Sn4 IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell. Research limitations/implications The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design. Practical implications This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology. Originality/value The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.

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