Pure Chemical Reduction of Tin Oxides to Metallic Tin by Atmospheric Plasma to Improve Interconnection Reflow of Pb-free Solders

2015 ◽  
Vol 2015 (1) ◽  
pp. 000725-000729
Author(s):  
Kang-Wook Lee ◽  
Katsuyuki Sakuma ◽  
Thomas Lombardi ◽  
Jason Rowland ◽  
David Lewison ◽  
...  

Tin alloys are widely used as solder for electronic interconnections. Tin solder surfaces tend to have tin oxides which need to be removed to improve the yield of interconnection reflow processes such as flip chip joining. Conventionally, a strong flux is employed to remove these oxides, however this process has the drawbacks of leaving flux residue which can cause underfill delamination or require a high-cost cleaning process. As solder bump volumes and bump-to-bump spacing decrease, these problems become more difficult to manage in manufacturing. We propose the use of Atmospheric Plasma to reduce these oxides from the bump surfaces to enable the use of very light fluxes, or no flux at all. This process has the advantages of plasma surface preparation without the cost and throughput penalty of vacuum plasma processes. Such a process can increase throughput and yield while reducing the cost. We describe an experiment in which tin foils were treated with a reducing-chemistry Atmospheric Plasma process and then analyzed with X-ray photoelectron spectroscopy (XPS) and Auger Electron Spectroscopy (AES). AES depth profile analyses indicate that the thickness of tin oxides was significantly reduced by the plasma. There was no evidence for any etching of underlying elemental tin. These results suggest that tin oxides are reduced to metallic tin without etching of the underlying tin metal. In another similar experiment using semiconductor chips with SnAg solders, XPS results suggest that the tin oxides were again reduced to metallic tin. In flip chip joining, the joining process with such Atmospheric Plasma-treated chips achieved high interconnect yield, even in the case of poor quality solder balls with excessive oxidation. It is our understanding that the pure chemical reduction of tin oxides with atmospheric plasma in ambient had not been previously reported.

2014 ◽  
Vol 2014 (1) ◽  
pp. 000783-000786 ◽  
Author(s):  
Farhang Yazdani

Silicon interposer is emerging as a vehicle for integrating dies with sub 50um bump pitch in 2.5D/3D configuration. Benefits of 2.5D/3D integration are well explained in the literature, however, cost and reliability is a major concern especially with the increase in interposer size. Among the challenges, reliability issues such as warpage, cracks and thermal-stresses must be managed, in addition, multi-layer build-up flip chip substrate cost and its impact on the overall yield must be considered. Because of these challenges, 2.5D/3D silicon interposer has developed a reputation as a costly process. To overcome the reliability challenges and cost associated with typical thin interposer manufacturing and assembly, a rigid silicon interposer type structure is disclosed. In this study, interposer with thickness of greater than 300um is referred to as rigid interposer. Rigid silicon interposer is directly assembled on PCB without the need for intermediary substrate. This eliminates the need for an intermediary substrate, thin wafer handling, wafer bonding/debonding procedures and Through Silicon Via (TSV) reveal processes, thus, substantially reducing the cost of 2.5D/3D integrated products while improving reliability. A 10X10mm2 rigid silicon interposer test vehicle with 310um thickness was designed and fabricated. BGA side of the interposer with 1mm ball pitch was bumped with eutectic solder balls through a reflow process. Interposer was then assembled on a 50X50mm2 FR-4 PCB. We present design and direct assembly of the rigid silicon interposer on PCB followed by temperature cycle results using CSAM images at 250, 500, 750 and 1000 cycles. It is shown that all samples successfully passed the temperature cycle stress test.


2020 ◽  
Vol 67 (1) ◽  
pp. 28-34
Author(s):  
Aleksandr V. Vinogradov ◽  
Aleksey V. Bukreev

When repairing and replacing electrical wiring in enterprises, the main difficulty is the lack or poor quality of documentation, plans for conductors laying. Distinguishing wires (cables) and their cores by the color of the shells or using tags attached to the ends is difficult if the shells have the same color and there are no tags. Devices and technical solutions used to identify wires and cables do not allow recognizing conductors without breaking the electrical circuit, removing insulation, and de-energizing the network. Searching for the right conductor is a time-consuming operation. (Research purpose) The research purpose is developing a new microcontroller device for identifying wires using an acoustic signal. (Materials and methods) Literature sources has been searched for devices for conductors identifying. (Results and discussion) The article proposes a method that involves feeding an acoustic signal to a wire at one point and capturing it at another, in order to recognize the desired wire. The article presents results of comparison of the developed microcontroller device for identifying conductors using an acoustic signal with known devices and methods for conductors recognizing. (Conclusions) The article reveals the shortcomings of existing methods and means of identifying wires and cables. Authors performed a theoretical calculation of the sound pressure in the conductor at a given distance. The article presents the calculation of speed of acoustic waves in conductors with different types of insulation. Authors designed a microcontroller device for identifying conductors using an acoustic signal and tested it. It was determined that the device increases the safety of work, reduces the cost of operating internal wiring and identification time; eliminates the violation of wire insulation, the need to disable electrical receivers. The convergence of theoretical calculations and experimental data was shown.


2009 ◽  
Vol 24 (8) ◽  
pp. 2520-2527 ◽  
Author(s):  
Yonghao Lu ◽  
Junping Wang ◽  
Yaogen Shen ◽  
Dongbai Sun

A series of Ti-B-C-N thin films were deposited on Si (100) at 500 °C by incorporation of different amounts of N into Ti-B-C using reactive unbalanced dc magnetron sputtering in an Ar-N2 gas mixture. The effect of N content on phase configuration, nanostructure evolution, and mechanical behaviors was studied by x-ray diffraction, x-ray photoelectron spectroscopy, Raman spectroscopy, high-resolution transmission electron microscopy, and microindentation. It was found that the pure Ti-B-C was two-phased quasi-amorphous thin films comprising TiCx and TiB2. Incorporation of a small amount of N not only dissolved into TiCx but also promoted growth of TiCx nano-grains. As a result, nanocomposite thin films of nanocrystalline (nc-) TiCx(Ny) (x + y < 1) embedded into amorphous (a-) TiB2 were observed until nitrogen fully filled all carbon vacancy lattice (at that time x + y = 1). Additional increase of N content promoted formation of a-BN at the cost of TiB2, which produced nanocomposite thin films of nc-Ti(Cx,N1-x) embedded into a-(TiB2, BN). Formation of BN also decreased nanocrystalline size. Both microhardness and elastic modulus values were increased with an increase of N content and got their maximums at nanocomposite thin films consisting of nc-Ti(Cx,N1-x) and a-TiB2. Both values were decreased after formation of BN. Residual compressive stress value was successively decreased with an increase of N content. Enhancement of hardness was attributed to formation of nanocomposite structure and solid solution hardening.


2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Jien Ye ◽  
Yi Wang ◽  
Qiao Xu ◽  
Hanxin Wu ◽  
Jianhao Tong ◽  
...  

AbstractPassivation of nanoscale zerovalent iron hinders its efficiency in water treatment, and loading another catalytic metal has been found to improve the efficiency significantly. In this study, Cu/Fe bimetallic nanoparticles were prepared by liquid-phase chemical reduction for removal of hexavalent chromium (Cr(VI)) from wastewater. Synthesized bimetallic nanoparticles were characterized by transmission electron microscopy, Brunauer–Emmet–Teller isotherm, and X-ray diffraction. The results showed that Cu loading can significantly enhance the removal efficiency of Cr(VI) by 29.3% to 84.0%, and the optimal Cu loading rate was 3% (wt%). The removal efficiency decreased with increasing initial pH and Cr(VI) concentration. The removal of Cr(VI) was better fitted by pseudo-second-order model than pseudo-first-order model. Thermodynamic analysis revealed that the Cr(VI) removal was spontaneous and endothermic, and the increase of reaction temperature facilitated the process. X-ray photoelectron spectroscopy (XPS) analysis indicated that Cr(VI) was completely reduced to Cr(III) and precipitated on the particle surface as hydroxylated Cr(OH)3 and CrxFe1−x(OH)3 coprecipitation. Our work could be beneficial for the application of iron-based nanomaterials in remediation of wastewater.


Materials ◽  
2020 ◽  
Vol 13 (3) ◽  
pp. 594 ◽  
Author(s):  
Mara Serrapede ◽  
Marco Fontana ◽  
Arnaud Gigot ◽  
Marco Armandi ◽  
Glenda Biasotto ◽  
...  

A simple, low cost, and “green” method of hydrothermal synthesis, based on the addition of l-ascorbic acid (l-AA) as a reducing agent, is presented in order to obtain reduced graphene oxide (rGO) and hybrid rGO-MoO2 aerogels for the fabrication of supercapacitors. The resulting high degree of chemical reduction of graphene oxide (GO), confirmed by X-Ray Photoelectron Spectroscopy (XPS) analysis, is shown to produce a better electrical double layer (EDL) capacitance, as shown by cyclic voltammetric (CV) measurements. Moreover, a good reduction yield of the carbonaceous 3D-scaffold seems to be achievable even when the precursor of molybdenum oxide is added to the pristine slurry in order to get the hybrid rGO-MoO2 compound. The pseudocapacitance contribution from the resulting embedded MoO2 microstructures, was then studied by means of CV and electrochemical impedance spectroscopy (EIS). The oxidation state of the molybdenum in the MoO2 particles embedded in the rGO aerogel was deeply studied by means of XPS analysis and valuable information on the electrochemical behavior, according to the involved redox reactions, was obtained. Finally, the increased stability of the aerogels prepared with l-AA, after charge-discharge cycling, was demonstrated and confirmed by means of Field Emission Scanning Electron Microscopy (FESEM) characterization.


Author(s):  
Chittaranjan Sahay ◽  
Suhash Ghosh ◽  
Pradeep Kumar Bheemarthi

This work describes a strategy to reduce the cost associated with poor quality, by reducing the parts per million defects by Defining, Measuring, Analyzing, Implementing and Controlling (DMAIC) the production process. The method uses a combination of principles of Six Sigma applications, Lean Manufacturing and Shanin Strategy. The process has been used in analyzing the manufacturing lines of a brake lever at a Connecticut automotive components manufacturing company for reducing the cost associated with the production of nonconforming parts. The analysis was carried out with the help of the data collected on nonconformance parts and the application of phase change rules from DMAIC (+). Data analysis was carried out on statistical process control softwares, MINITAB and SPC XL 2000. Although, the problem of tight bushing existed on only one line of the brake lever assembly, this problem solving approach has solved the tight bushing problems on all assembly and alternates lines in a time- and cost-effective way.


2001 ◽  
Vol 668 ◽  
Author(s):  
J. Fritsche ◽  
S. Gunst ◽  
A. Thiβen ◽  
R. Gegenwart ◽  
A. Klein ◽  
...  

ABSTRACTTin dioxide (SnO2) coated glass is the commonly used substrate for thin film solar cells based on CdTe absorbers. We have investigated the properties of the CdS/SnO2 interface by X-ray and ultraviolet photoelectron spectroscopy. SnO2 coated glass substrates as used for solar cell preparation were cleaned by different procedures such as derinsing, sputtering, heating and annealing in oxygen atmosphere. Different surface properties with a strongly dependent number of defects in the SnO2 band gap are identified. CdS films were deposited stepwise by thermal evaporation to determine the electronic interface properties for different surface preparation conditions. Comparative barrier heights at the CdSSnO2 contact are found for most surface pretreatments. The Fermi level position in these cases is situated in the SnO2 band gap. A different interface behaviour is determined for sputter cleaned SnO2 surfaces, which is attributed to the formation of oxygen vacancies during sputtering and subsequent formation of an interfacial SnOxSy compound.


Author(s):  
Pushkraj Tumne ◽  
Vikram Venkatadri ◽  
Santosh Kudtarkar ◽  
Michael Delaus ◽  
Daryl Santos ◽  
...  

Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.


2002 ◽  
Vol 3 (2) ◽  
pp. 159-182 ◽  
Author(s):  
Lou Magritzer ◽  
Jichao Xu

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