Accurate Prediction of Thermal Resistance of FET by Detailed Modeling of Heat Generation and Backend Stackup

2012 ◽  
Vol 2012 (1) ◽  
pp. 000848-000856
Author(s):  
Qun Wan ◽  
Don Willis ◽  
Daniel Jin
Keyword(s):  
Thermal Resistance ◽  
Heat Generation ◽  
Field Effect Transistor ◽  
Heat Dissipation ◽  
Electrical Potential ◽  
Drain Side ◽  
Significant Difference ◽  
Electrical Potential Field ◽  
Effect Transistor ◽  
Gate Edge

In typical thermal modeling of a FET (field effect transistor) structure, the power could be modeled as the heat generation, which is averaged under the entire gate length (gate averaged). However, it is found from the electrical potential field within the channel that the heat generation is actually distributed all the way from source to drain with a heavy concentration around the gate edge at the drain side. In a typical case, the peak of the heat distribution is almost four times of the gate averaged. Therefore, accurate modeling of the heat generation averaging over a much smaller region near the gate edge (edge averaged) makes a significant difference. This paper focuses on the comparison of the edge averaged versus the gate averaged modeling development. Furthermore, the detailed topology of the backend stackup layers and their relative impacts on heat dissipation paths are evaluated and the practical simplification is proposed in the modeling development. The result shows that, for a single gate FET die, the thermal resistance is found to be 26% more than that of the gate averaged approach. For a multiple gate FET die, both methods give the same surface temperature on the top surface layer. However, the temperature difference (ΔTjs) between the junction and the top surface is different between the two heat averaging approaches and the edge averaged approach prediction doubles that of the gate averaged approach. It is also found that ΔTjs is independent of number of gates and only depends on the backend stackup details between source and drain.

scholarly journals Sensing and Reliability Improvement of Electrostatic-Discharge Transient by Discrete Engineering for High-Voltage 60-V n-Channel Lateral-Diffused MOSFETs with Embedded Silicon-Controlled Rectifiers

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3340
Author(s):  
Shen-Li Chen ◽  
Yi-Cih Wu
Keyword(s):  
High Voltage ◽  
Field Effect Transistor ◽  
Electrostatic Discharge ◽  
Reference Sample ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Physical Parameters ◽  
Reliability Improvement ◽  
Drain Side ◽  
Effect Transistor

High-voltage n-channel lateral-diffused metal-oxide-semiconductor field-effect transistor (nLDMOS) components, fabricated by a TSMC 0.25-m 60-V bipolar-CMOS-DMOS (BCD) process with drain-side embedded silicon-controlled rectifier (SCR) of the n-p-n-arranged and p-n-p-arranged types, were investigated, in order to determine the devices’ electrostatic discharge (ESD)-sensing behavior and capability by discrete anode engineering. As for the drain-side n-p-n-arranged type with discrete-anode manners, transmission–line–pulse (TLP) testing results showed that the ESD ability (It2 value) was slightly upgraded. When the discrete physical parameter was 91 rows, the optimal It2 reached 2.157 A (increasing 17.7% compared with the reference sample). On the other hand, the drain-side SCR p-n-p-arranged type with discrete-anode manner had excellent SCR behavior, and its It2 values could be increased to >7 A (increasing >281.9% compared with the reference DUT). Moreover, under discrete anode engineering, the drain-side SCR n-p-n-arranged and p-n-p-arranged types had clearly higher ESD ability, except for the few discrete physical parameters. Therefore, using the anode discrete engineering, the ESD dissipation ability of a high-voltage (HV) nLDMOS with drain-side SCRs will have greater effectiveness.

Novel Reconfigurable Field-Effect Transistor With Asymmetric Spacer Engineering at Drain Side

2020 ◽  
Vol 67 (2) ◽  
pp. 751-757 ◽  
Author(s):  
Yan Yao ◽  
Yabin Sun ◽  
Xiaojin Li ◽  
Yanling Shi ◽  
Ziyu Liu
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Drain Side ◽  
Effect Transistor

A NOVEL GRAPHENE NANO-RIBBON FIELD EFFECT TRANSISTOR WITH SCHOTTKY TUNNELING DRAIN AND OHMIC TUNNELING SOURCE

2013 ◽  
Vol 27 (26) ◽  
pp. 1350189 ◽  
Author(s):  
SEYED SALEH GHOREISHI ◽  
KAMYAR SAGHAFI ◽  
MOHAMMAD KAZEM MORAVVEJ-FARSHI
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Schottky Contact ◽  
Graphene Nanoribbon ◽  
Tunneling Fet ◽  
Ambipolar Behavior ◽  
Drain Side ◽  
Mode Space ◽  
Conventional Structure ◽  
Effect Transistor

In this paper, we propose a novel tunneling graphene nanoribbon field effect transistor by modification of the conventional structure in a way that its drain high-doped extension part is replaced by lightly linear doped region. Then the proposed structure has a Schottky contact at the drain side. As the source contact is ohmic and the drain contact is Schottky, this structure is called Schottky–Ohmic tunneling graphene nanoribbon field effect transistor. Electrical behaviors of the proposed device are investigated by mode space nonequilibrium Green's function (NEGF) formalism in the ballistic limit. Simulation results show that without increasing transistor length, I OFF , I ON /I OFF , ambipolar behavior, delay time and PDP of the proposed structure improve, in comparison with the conventional tunneling graphene nanoribbon field effect transistor with the same dimension. Also subthreshold swing which is one of the evident characteristics of the tunneling FET is preserved in this structure.

scholarly journals SIMULATING CURRENT - VOLTAGE CHARACTERISTICS OF MOLECULAR TRANSISTOR FIELD EFFECT TRANSISTOR

2009 ◽  
Vol 12 (13) ◽  
pp. 5-12
Author(s):  
Hien Sy Dinh ◽  
Trung Hoang Huynh
Keyword(s):  
Field Effect ◽  
High Speed ◽  
Field Effect Transistor ◽  
Promising Alternative ◽  
Current Voltage ◽  
Significant Difference ◽  
Current Voltage Characteristics ◽  
Effect Transistor ◽  
Non Equilibrium Green’S Function ◽  
Material Temperature

Molecular Field Effect Transistor (MFET) is a promising alternative candidate of traditional MOSFET in future due to its small size, low power consumption and high speed. In this work, we introduce a model of three-terminal MFET. The structure of the MFET is in shape like traditional MOSFET, but its conductive channel is replaced by a benzene-1,4-dithiolate molecule. We use non-equilibrium Green's function method to compute transport function of charges and ultimately, the current-voltage (1-V) characteristics. The program is written by using graphic user guide (GUI) in Matlab. We have found significant difference of I-V characteristics between MOSFET and MFET. In addition, impacts of types of material, temperature, and bias on I-V characteristics of the MFET have been considered. Using GUI in Matlab, obtained results of simulations are intuitively displayed.

scholarly journals Leakage Mitigation in NW FET using Negative Schottky Junction Drain and its Process Variation Analysis

2021 ◽  
Author(s):  
Mohd Rizwan Uddin Shaikh ◽  
Sajad A Loan ◽  
Abdullah G Alharbi
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Schottky Barrier Height ◽  
Process Variation ◽  
Process Variations ◽  
Schottky Junction ◽  
Variation Analysis ◽  
Drain Side ◽  
Band To Band Tunneling ◽  
Effect Transistor

Abstract In this work, a Schottky junction on the drain side employing low workfunction (WF) metal is proposed as a method to suppress the OFF-state leakage in nanowire (NW) field-effect transistor (FET). Instead of a highly n+ doped drain, low WF metal with negative electron Schottky-barrier height (SBH) as a drain minimizes the lateral band-to-band tunneling (L-BTBT) considerably. L-BTBT is the movement of carriers (holes) from the drain conduction band (CB) into the channel valence band (VB) during the OFF-state. Impact of varying WF at channel-drain junction on the device characteristics is studied. It is observed that SBH60 eV is required to mitigate L-BTBT compared to the conventionally-doped and junctionless (JL) NW counterpart. Furthermore, unlike L-BTBT, leakage in NW Schottky-drain (SD) comprises of holes tunneling through the SB from the metal drain into the channel and termed as the lateral SB tunneling (L-SBT). In contrast to JL NW FET, the process variation immunity (varying channel doping, NCh and NW diameter, dNW ) and the ON-state current of the proposed device is not compromised at the expense of lower OFF-state LSBT. Instead, the device is less susceptible to process variations and retains the ON-state performance of the NW MOSFET. For a ±20% change in NCh, ∆IOF F /IOF F of 7% compared to 97% in NW JL FET is observed.

Improvement in Self-Heating Characteristic by Utilizing Sapphire Substrate in Omega-Gate-Shaped Nanowire Field Effect Transistor for Wearable, Military, and Aerospace Application

2021 ◽  
Vol 21 (5) ◽  
pp. 3092-3098
Author(s):  
Young Suh Song ◽  
Hyunwoo Kim ◽  
Junsu Yu ◽  
Jongho Lee
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Heat Dissipation ◽  
Silicon On Insulator ◽  
The Self ◽  
Self Heating ◽  
Aerospace Applications ◽  
Radiation Resistant ◽  
Effect Transistor

In this study, we propose an omega-shaped-gate nanowire field effect transistor (ONWFET) with a silicon-on-sapphire (SOS) substrate. In order to investigate improvements in the self-heating characteristic with the use of a SOS substrate, the lattice temperature is examined using a Synopsys Sentaurus 3D Technology computer-aided design (TCAD) simulator with the results compared to those with a silicon-on-insulator (SOI) substrate. To validate the proposed structure with the SOS substrate, the locations of hot spots and heat dissipation paths (heat sinks) depending on the substrate materials are also analyzed. The electrical characteristics, specifically the on-current (Ion), off-current (Ioff), and subthreshold swing (SS), were investigated as well. Hence, it is demonstrated here that incorporating a SOS substrate can improve both the self-heating characteristic and the SS at the same time. Therefore, enhanced logic devices are feasible if using an ONWFET with a SOS substrate. Examples include wearable devices and military and future aerospace applications achieved by the radiation-resistant material Al2O3 that has high thermal conductivity.

scholarly journals Analysis on Tunnel Field-Effect Transistor with Asymmetric Spacer

2020 ◽  
Vol 10 (9) ◽  
pp. 3054
Author(s):  
Hyun Woo Kim ◽  
Daewoong Kwon
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Model Parameters ◽  
Tunnel Fet ◽  
Drain Side ◽  
Fringing Field ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
The Impact

Tunnel field-effect transistor (Tunnel FET) with asymmetric spacer is proposed to obtain high on-current and reduced inverter delay simultaneously. In order to analyze the proposed Tunnel FET, electrical characteristics are evaluated by technology computer-aided design (TCAD) simulations with calibrated tunneling model parameters. The impact of the spacer κ values on tunneling rate is investigated with the symmetric spacer. As the κ values of the spacer increase, the on-current becomes enhanced since tunneling probabilities are increased by the fringing field through the spacer. However, on the drain-side, that fringing field through the drain-side spacer increases ambipolar current and gate-to-drain capacitance, which degrades leakage property and switching response. Therefore, the drain-side low-κ spacer, which makes the low fringing field, is adapted asymmetrically with the source-side high-κ spacer. This asymmetric spacer results in the reduction of gate-to-drain capacitance and switching delay with the improved on-current induced by the source-side high-κ spacer.

Preparation of TEM samples by focused ion beams

1995 ◽  
Vol 53 ◽  
pp. 518-519
Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Field Effect Transistor ◽  
High Spatial Resolution ◽  
Ion Beam ◽  
Ion Beams ◽  
Focused Ion Beams ◽  
Precise Location ◽  
Effect Transistor ◽  
Circuit Technology

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.

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