scholarly journals Analysis on Tunnel Field-Effect Transistor with Asymmetric Spacer

2020 ◽  
Vol 10 (9) ◽  
pp. 3054
Author(s):  
Hyun Woo Kim ◽  
Daewoong Kwon
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Model Parameters ◽  
Tunnel Fet ◽  
Drain Side ◽  
Fringing Field ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
The Impact

Tunnel field-effect transistor (Tunnel FET) with asymmetric spacer is proposed to obtain high on-current and reduced inverter delay simultaneously. In order to analyze the proposed Tunnel FET, electrical characteristics are evaluated by technology computer-aided design (TCAD) simulations with calibrated tunneling model parameters. The impact of the spacer κ values on tunneling rate is investigated with the symmetric spacer. As the κ values of the spacer increase, the on-current becomes enhanced since tunneling probabilities are increased by the fringing field through the spacer. However, on the drain-side, that fringing field through the drain-side spacer increases ambipolar current and gate-to-drain capacitance, which degrades leakage property and switching response. Therefore, the drain-side low-κ spacer, which makes the low fringing field, is adapted asymmetrically with the source-side high-κ spacer. This asymmetric spacer results in the reduction of gate-to-drain capacitance and switching delay with the improved on-current induced by the source-side high-κ spacer.

scholarly journals Impactful Study of F-shaped Tunnel FET

2021 ◽  
Author(s):  
PRABHAT SINGH ◽  
DHARMENDRA SINGH YADAV
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Source Region ◽  
Gate Oxide ◽  
Crowding Effect ◽  
Turn On ◽  
Tunnel Fet ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
The Impact

Abstract In this proposed work, a novel single gate F-shaped channel tunnel field effect transistor (SG-FC-TFET) is proposed and investigated. The impact of thickness of the source region and lateral tunneling length between the gate oxide and edge of the source region on analog and radio frequency parameters are investigated with appropriate source and drain lateral length through the 2D-TCAD tool. The slender shape of the source enhanced the electric le crowding effect at the corners of the source region which reflect in term of high On-current (Ion). The Ion of proposed device is increased up to 10-4 A=μm with reduced sub-threshold swing (SS) is 7.3 mV/decade and minimum turn-ON voltage (Von = 0.28 V). The analog/RF parameters of SG-FC-TFET are optimized.

Temperature Sensitivity Analysis of Extended Source Double Gate Tunnel Field Effect Transistor

2021 ◽  
Author(s):  
Dharmender Nishad ◽  
Kaushal Nigam ◽  
Satyendra Kumar
Keyword(s):  
Temperature Sensitivity ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Of Temperature ◽  
Double Gate ◽  
Extended Source ◽  
Temperature Variations ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract Temperature-induced performance variation is one of the main concerns of the conventional stack gate oxide double gate tunnel field-effect transistor (SGO-DG-TFET). In this regard, we investigate the temperature sensitivity of extended source double gate tunnel field-effect transistor (ESDG-TFET). For this, we have analyzed the effect of temperature variations on the transfer characteristics, analog/RF, linearity and distortion figure of merits (FOMs) using technology computer aided design (TCAD) simulations. Further, the temperature sensitivity performance is compared with conventional SGO-DG-TFET. The comparative analysis shows that ESDG-TFET is less sensitive to temperature variations compared to the conventional SGO-DG-TFET. Therefore, this indicates that ESDG-TFET is more reliable for low-power, high-frequency applications at a higher temperature compared to conventional SGO-DG-TFET.

scholarly journals Demonstration of Fin-Tunnel Field-Effect Transistor with Elevated Drain

Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 30 ◽  
Author(s):  
Jang Hyun Kim ◽  
Hyun Woo Kim ◽  
Garam Kim ◽  
Sangwan Kim ◽  
Byung-Gook Park
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Electrical Performance ◽  
Control Group ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation ◽  
High Level ◽  
Aided Design

In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its electrical performance. As a result, it shows high-level ON-state current (ION) and low-level OFF-state current (IOFF); ambipolar current (IAMB). In detail, its ION is enhanced by 24 times more than that of Si control group and by 6 times more than of SiGe control group. The IAMB can be reduced by up to 900 times compared with the SiGe control group. In addition, technology computer-aided design (TCAD) simulation is performed to optimize electrical performance. Then, the benchmarking of ON/OFF current is also discussed with other research group’s results.

scholarly journals Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

2021 ◽  
Author(s):  
Garima Jain ◽  
Ravinder Singh Sawhney ◽  
Ravinder Kumar ◽  
Amit Saini
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Subthreshold Swing ◽  
Short Channel ◽  
Tunneling Mechanism ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to a gate length of 12nm with Contact poly pitch (CPP) of 48nm is simulated. NS-TFET device is investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism with a P-I-N layout has been incorporated in the stacked nanosheet devices. The asymmetric design technique for doping has been used for optimum results. NS-TFET provides a low leakage current of order10-16 A, an excellent subthreshold swing (SW) of 23mv/decade, and negligible drain induced barrier lowering (DIBL) having a value of 10.5 mv/V. The notable ON to OFF current ratio of the order of 1011 has been achieved. The device exhibits a high transconductance of 3.022x10-5 S at the gate to source voltage of 1V. NS-TFET shows tremendous improvement in short channel effects (SCE) and is a good option for advanced technologies.

I-Shaped SiGe Fin Tunnel Field-Effect Transistor with High ION/IOFF Ratio

2020 ◽  
Vol 20 (7) ◽  
pp. 4298-4302
Author(s):  
Ryoongbin Lee ◽  
Junil Lee ◽  
Kitae Lee ◽  
Soyoun Kim ◽  
Sihyun Kim ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Channel Width ◽  
Condensation Process ◽  
Performance Improvements ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design ◽  
Effective Channel

In this paper, we propose an I-shaped SiGe fin tunnel field-effect transistor (TFET) and use technology computer aided design (TCAD) simulations to verify the validity. Compared to conventional Fin TFET on the same footprint, a 27% increase in the effective channel width can be obtained with the proposed TFET. The proposed Fin TFET was confirmed to have 300% boosted on-current (I on), 25% reduced subthreshold swing (SS), and 52% lower off-current (I off) than conventional Fin TFET through TCAD simulation results. These performance improvements are attributed to increased effective channel width and enhanced gate controllability of the I-shaped fin structure. Furthermore, the fabrication process of forming an I-shaped SiGe fin is also presented using the SiGe wet etch. By optimizing the Ge condensation process, an I-shaped SiGe fin with a Ge ratio greater than 50% can be obtained.

scholarly journals Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network

Crystals ◽  
2021 ◽  
Vol 11 (2) ◽  
pp. 128
Author(s):  
Zhihua Zhu ◽  
Zhaonian Yang ◽  
Xiaomei Fan ◽  
Yingtao Zhang ◽  
Juin Jei Liou ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Source Region ◽  
Potential Candidate ◽  
Protection Scheme ◽  
Esd Protection ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing a secondary path in a whole-chip electrostatic discharge (ESD) protection network. In this paper, the ESD characteristics of a traditional point TFET, a line TFET and a Ge-source TFET are investigated using technology computer-aided design (TCAD) simulations, and an improved TFET-based whole-chip ESD protection scheme is proposed. It is found that the Ge-source TFET has a lower trigger voltage and higher failure current compared to the traditional point and line TFETs. However, the Ge-source TFET-based secondary path in the whole-chip ESD protection network is more vulnerable compared to the primary path due to the low thermal instability. Simulation results show that choosing the proper germanium mole fraction in the source region can balance the discharge ability and thermal failure risk, consequently enhancing the whole-chip ESD robustness.

scholarly journals Analysis of Current Variation with Work Function Variation in L-Shaped Tunnel-Field Effect Transistor

Micromachines ◽  
2020 ◽  
Vol 11 (8) ◽  
pp. 780
Author(s):  
Jang Hyun Kim ◽  
Hyun Woo Kim ◽  
Young Suh Song ◽  
Sangwan Kim ◽  
Garam Kim
Keyword(s):  
Work Function ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Tunnel Barrier ◽  
Entire Area ◽  
Current Variation ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

In this paper, an investigation is performed to analyze the L-shaped tunnel field-effect transistor (TFET) depending on a gate work function variation (WFV) with help of technology computer-aided design (TCAD) simulation. Depending on the gate voltage, the three variations occur in transfer curves. The first one is the on-state current (ION) variation, the second one is the hump current (IHUMP) variation, and the last one is ambipolar current (IAMB) variation. According to the simulation results, the ION variation is sensitive depending on the size of the tunneling region and could be reduced by increasing the tunneling region. However, the IHUMP and IAMB variations are relatively irrelevant to the size of the tunneling region. In order to analyze the cause of this difference, we investigated the band-to-band tunneling (BTBT) rate according to WFV cases. The results show that when ION is formed in L-shaped TFET, the BTBT rate relies on the WFV in the whole region of the gate because the tunnel barrier is formed in the entire area where the source and the gate meet. On the other hand, when the IHUMP and IAMB are formed in L-shaped TFET, the BTBT rate relies on the WFV in the edge of the gate.

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