Electromigration Reliability of Glass Ceramic Multilayer Substrate with Various Surface Finishes

2012 ◽  
Vol 2012 (1) ◽  
pp. 000503-000509
Author(s):  
Hiroshi Matsumoto ◽  
Akira Wakazaki ◽  
Shingo Sato ◽  
Takashi Okunosono ◽  
Chihiro Makihara
Keyword(s):  
Life Cycle ◽  
Current Density ◽  
Glass Ceramic ◽  
High Speed ◽  
Flip Chip ◽  
Solder Joints ◽  
Diffusion Rate ◽  
Ceramic Substrate ◽  
Solder Bumps ◽  
Glass Ceramic Substrate

The process speed of high-end servers and supercomputers are steadily increasing. As a result, the backbone of the high speed processing, such as high-end LSI (flip-chip type), and associated substrate circuits is also becoming more dense and miniaturized, while supporting higher current densities. However, recent studies indicate that the higher current density triggers an electromigration (EM) at the solder bumps connecting the under bump metallurgy (UBM) of the flip-chip pad (e.g. Ni) and substrate pads (e.g. Ni/Au). This electromigration leads to voids within the solder joints, which may result in an open circuit. As of result, the life-cycle of the packaged devices is shortened. Thus solution to the EM issue is critical. To respond to such concerns, we have studied the mechanism of the void development, by closely examining differences in diffusion rate among the connective metals - within the pads and the solders. We have mitigated the EM occurrence by reducing the differences in diffusion rate by utilizing high purity Cu for the substrate metallization pads, Cu exhibits a diffusion rate similar to Sn used in solder bumps. Also, solder wettability was improved by utilizing a solder on pad (SOP) construction. As of result we were able to successfully demonstrate an improved life-cycle of the flip-chip solder joints, while accommodating a higher current density. Furthermore, a glass ceramic substrate was used for our study. Since this particular glass ceramic substrate has a coefficient of thermal expansion of 11.8ppm/K, there is an improvement in 1st and 2nd level reliabilities associated with thermal stress from device heat generation. At the same time, it possesses a dielectric constant of 5.8, which is conductive with superior electrical performance (high speed and high frequency). Thus, this glass ceramic substrate is capable of supporting increases in current density, while sustaining high reliability.

Long-term Electromigration Study of Lead-Free Flip-Chips with Solder Bumps with 50 μm or 60 μm Diameter Employing ENIG Surface Finish on Both Chip and Substrate Side

2013 ◽  
Vol 2013 (1) ◽  
pp. 000523-000530 ◽  
Author(s):  
Marek Gorywoda ◽  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
...  
Keyword(s):  
Current Density ◽  
Surface Finish ◽  
Flip Chip ◽  
Solder Joints ◽  
High Current Density ◽  
Life Time ◽  
Lead Free ◽  
Cathode Side ◽  
Solder Bumps

Electromigration behaviour of Pb-free solder joints in flip-chip interconnects is usually studied in highly accelerated, short-term experiments using high current density and temperature. Failures typically occur in bumps which are in cathode contact at the chip side. There are only a few published studies in which Electroless Ni-P/Immersion Au (ENIG) surface finish was used as under-bump-metallization (UBM) structure, e.g. [5]. This paper deals with the long-term electromigration behaviour of Pb-free SAC305 flip-chip solder joints with a pitch of 100 μm and solder bump diameters of 50 μm or 60 μm, respectively. The ENIG surface finish was used on both the substrate and chip side. Test specimens were subjected to several levels of temperature and current density and tested up to 16,000 hours. The life time data is summarized using Weibull and lognormal distribution. The microstructure changes of interconnects in failed samples were subsequently investigated by SEM and EDX. Interconnects had failed due to consumption of Nickel, voids caused by electromigration, and Kirkendall void formation in the Ni-P-layer. The damage was asymmetric in respect to the current flow direction through the solder bumps and was most pronounced at the cathode side. Unexpectedly, however, the most severe damage occurred at the substrate and not at the chip side. We could show that - allowing for a few guidelines - lead-free flip-chip solder joints with 50 μm or 60 μm diameter have a sufficient electromigration life time for most applications.

Electromigration in Solder Joints for High Temperature Flip-Chip Application

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002481-002506
Author(s):  
Mathias Nowottnick ◽  
Andreas Fix
Keyword(s):  
High Temperature ◽  
Current Density ◽  
Flip Chip ◽  
Solder Joints ◽  
Metallographic Analysis ◽  
Solder Alloys ◽  
Directed Movement ◽  
Cross Sectional ◽  
Current Densities ◽  
And Migration

The electromigration effects in chip metallization and wire bonds are well known and detailed investigated. Current density could be extremely high because of the small size of the cross sectional area of conductors. This can cause a migration of metal atoms toward the electrical field, so current densities up to 106 A/cm2 are possible. In comparison with chip structures are the usual solder joints of flip chips relatively thick. But the homologue temperature of solder alloys, typically based on tin, is also much higher than for gold or aluminum wires. For instance a SAC solder alloy is naturally preheated up to 0.6 homologue temperature, for high temperature application with 125 °C operating temperature even more than 0.8. This means, that atoms are very agile and a directed movement needs only lower field strength. Additionally is the specific resistance of solder alloys tenfold higher than for aluminum, copper or silver. So is the self-heating of solder joints not negligible. This contribution shows the test results of flip-chip assemblies, loaded with different current densities and stored at 125 °C ambient temperature. At the end of life of a significant number of test chips, a metallographic analysis shows the causing failure effects and weak spots of assemblies. Accompanying simulations help to explain the interaction between current density and migration effects.

High Productivity Thermo-Compression Flip Chip Bonding

2014 ◽  
Vol 2014 (1) ◽  
pp. 000100-000106
Author(s):  
Tom Colosimo ◽  
Horst Clauberg ◽  
Evan Galipeau ◽  
Matthew B. Wasserman ◽  
Michael Schmidt-Lange ◽  
...  
Keyword(s):  
High Speed ◽  
Large Scale ◽  
Flip Chip ◽  
Solder Joints ◽  
Rapid Heating ◽  
Temperature Cycle ◽  
Temperature Uniformity ◽  
Heating Rates ◽  
Heating And Cooling ◽  
Chip Technology

Advancements in electronic packaging performance and cost have historically been driven by higher integration primarily provided by fab shrinks that has followed the well-known Moore's law. However, due to the tremendous and continuously increasing cost of building new fabs, the performance/cost improvements achieved via node shrinks are negated. This leaves packaging innovation as the vehicle to achieve future cost-performance improvements. This has initiated a More-than-Moore idea that has led to vigorous R&D in packaging. Advanced packages which employ ultra-fine pitch flip chip technology for chip-to-substrate, chip-to-chip, or chip-to-interposer for the first level interconnect have been developed as an answer to obtaining higher performance. However, the costs are too high as compared to traditional wire bonding. The status today is that the fundamental technical hurdles of manufacturing the new advanced packages have been solved, but cost reduction and yield improvements have to be addressed for large-scale adoption into high volume manufacturing. In traditional flip chip assembly silicon chips are tacked onto a substrate and then the solder joints are melted and mass reflowed in an oven. This mass reflow technique is troublesome as the pitch of the solder bumps become finer. This is due to the large differences in the thermal expansion coefficient of the die and the substrate, which creates stress at the solder joints and warpage of the package when the die and substrate are heated and cooled together. To mitigate and resolve this issue, thermo-compression bonders have been developed which locally reflow the solder without subjecting the entire substrate to the heating and cooling cycle. This requires that the bondhead undergo heating past the melting point of solder and then cooling down to a low enough temperature to pick the next die from the wafer that is mounted to tape. Machines in the market today can accomplish this temperature cycle in 7 to 15 seconds. This is substantially slower than the standard flip chip process which leads to high cost and is delaying the introduction of these new packages. This paper shows a flip chip bonder with a new heating and cooling concept that will radically improve the productivity of thermo-compression bonding. Data and productivity cycles from this new bond head with heating rates of over 200°C/sec and cooling of faster than 100°C/sec are revealed. Experimental results are shown of exceptional temperature accuracy across the die of 5°C throughout the cycle and better than 3°C at the final heating stage. The high speed thermo-compression bonds are analyzed and the efficacy of the new concept is proven. Excellent temperature uniformity while heating rapidly is an absolute necessity for enabling good solder joints in a fast process. Without good temperature uniformity, additional dwell times need to be incorporated to allow heat to flow to all of the joints, negating any benefits from rapid heating. Whereas the current state-of-that-art is often to program temperature in steps, this bonder can be commanded and accurately follows more complex temperature profiles with great accuracy. Examples of how this profiling can be used to enhance the uniformity and integrity of the joints with non-conductive pastes, film, and without underfill along with the associated productivity improvements will be shown. Tests that show portability across platforms that will lead to set up time and yield improvements and are identified and quantified. Additionally new ideas for materials and equipment development to further enhance productivity and yield are explored.

Large scale multilayer glass-ceramic substrate for supercomputer

1990 ◽  
Vol 13 (4) ◽  
pp. 751-758 ◽  
Author(s):  
Y. Shimada ◽  
Y. Kobayashi ◽  
K. Kata ◽  
M. Kurano ◽  
H. Takamizawa
Keyword(s):  
Glass Ceramic ◽  
Large Scale ◽  
Ceramic Substrate ◽  
Glass Ceramic Substrate

Low Firing Temperature Multilayer Glass-Ceramic Substrate

1983 ◽  
Vol 6 (4) ◽  
pp. 382-388 ◽  
Author(s):  
Y. Shimada ◽  
K. Utsumi ◽  
M. Suzuki ◽  
H. Takamizawa ◽  
M. Nitta ◽  
...  
Keyword(s):  
Firing Temperature ◽  
Glass Ceramic ◽  
Ceramic Substrate ◽  
Glass Ceramic Substrate
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