scholarly journals Cu Pillar Bump Development for 7-nm Chip Package Interaction (CPI) Technology

2020 ◽  
Vol 17 (1) ◽  
pp. 1-8
Author(s):  
Lei Fu ◽  
Milind Bhagavat ◽  
Cheryl Selvanayagam ◽  
Ken Leong ◽  
Ivor Barber
Keyword(s):  
Coming Out ◽  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Development Program ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Power Performance ◽  
Cu Pillar ◽  
Solder Bumps

Abstract Power, performance, and area gains are important metrics driving the complementary metal–oxide–semiconductor (CMOS) technology from older nodes to newer ones. Over past several decades, a steady downscaling of feature sizes of CMOS technology has been a leading force enabling continual improvement in circuit speeds and cost per functionality. Increase in functionality drives larger number of inputs/outputs (I/Os), and the scaling-driven small intellectual property (IP) block sizes force these larger number of I/Os to be accommodated by reduction of I/O pitches. The result is an unrelenting pressure to reduce bump pitches from one generation of CMOS to another. In contrast to 14-nm/16-nm nodes which used 150-um bump pitch coming out of a die, for 7-nm node, the industry is targeting 130-um bump pitch for high performance devices. With this pitch reduction, conventional tin/silver (SnAg) solder bumps face limitations in terms of bridging. Cu pillar bumps are the best candidate for smaller bump pitches. However, for large die sizes prevalent in high-performance computing (HPC), the Cu pillar bumps will induce higher stress on the silicon resulting in higher risks of extremely low K (ELK) cracking. If copper pillar bumps are not properly developed, then there is a risk of marginal reliability in terms of chip package interaction. The situation becomes even more dire in large die sizes, where coefficient of thermal expansion mismatch between silicon and laminate substrate magnifies the stress. The present article discusses successful development of Cu pillar bumps for 7-nm technology. The development program included a 2-step development path. In the first step, extensive thermomechanical modeling was carried out to find optimal design of copper pillar bump for robustness of interactions with 7-nm back end of line ELK layers. In the second step, a 460-mm2 7-nm Silicon test vehicle was fabricated, and its assembly process was optimized to characterize the copper pillar bumps and prove their extended reliability on 7-nm silicon. As a result of this development, copper pillar technology has been qualified on Advanced Micro Devices (AMD) products. Today, copper pillar is a fully integral part of AMD's ever-growing 7-nm product offering in HPC.

Cu pillar bump development for 7nm Chip package interaction (CPI) technology

2019 ◽  
Vol 2019 (1) ◽  
pp. 000176-000182 ◽  
Author(s):  
Lei Fu ◽  
Milind Bhagavat ◽  
Cheryl Selvanayagam ◽  
Ken Leong ◽  
Ivor Barber
Keyword(s):  
High Performance Computing ◽  
Coming Out ◽  
High Performance ◽  
Development Program ◽  
Cmos Technology ◽  
Power Performance ◽  
Cu Pillar ◽  
Solder Bumps ◽  
Cte Mismatch ◽  
Performance Computing

Abstract Power, performance, and area gains are important metrics driving the CMOS technology from older nodes to newer ones. Over past several decades, a steady downscaling of feature sizes of CMOS technology has been a leading force enabling continual improvement in circuit speeds and cost per functionality. Increase in functionality drives larger number of I/Os, and the scaling driven small IP block sizes force these larger number of I/Os to be accommodated by reduction of I/O pitches. The result is an unrelenting pressure to reduce bump pitches from one generation of CMOS to another. In contrast to 14nm/16nm nodes which used 150um bump pitch coming out of a die, for 7nm node the industry is targeting 130um bump pitch for high performance devices. With this pitch reduction, conventional SnAg solder bumps face limitations in terms of bridging. Cu pillar bumps are the best candidate for smaller bump pitches. However, for large die sizes prevalent in High Performance Computing, the Cu pillar bumps will induce higher stress on the silicon resulting in higher risks of ELK cracking. If copper pillar bumps are not properly developed, then there is a risk of marginal reliability in terms of chip package interaction. The situation becomes even more dire in large die sizes, where CTE mismatch between silicon and laminate substrate magnifies the stress. The present paper discusses successful development of Cu pillar bumps for 7nm technology. The development program included a 2-step development path. In the first step, extensive thermo-mechanical modeling was done to find optimal design of copper pillar bump for robustness of interactions with 7nm BEOL ELK layers. In the second step, a 460 mm2 7nm Silicon test Vehicle was fabricated and its assembly process was optimized to characterize the copper pillar bumps and prove their extended reliability on 7nm silicon. As a result of this development, copper pillar technology has been qualified on AMD products. Today, copper pillar is a fully integral part of AMD's ever-growing 7nm product offering in High Performance Computing.

scholarly journals Design and Implementation of High Performance and Low Power Mixed Logic Line Decoders

2019 ◽  
Vol 8 (6S4) ◽  
pp. 635-640
Keyword(s):  
High Performance ◽  
Data Transfer ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Analog To Digital ◽  
Delay Performance ◽  
And Performance ◽  
Almost All

The decoders are widely used in the logical circuits, data transfer circuits and analog to digital conversions. A mixed logic design methods for the line decoders are used to combining the transmission gate logic, pass transistor logic, and complementary metal-oxide semiconductor (CMOS) technology provides desired operation and performance. A novel topology is presented for the 2 to 4 decoder requires a fourteen transistor topology aiming on reducing the transistor count and operating power and a fifteen transistor topology aiming on high power and low delay performance. The standard and inverting decoders are designed in each of the case, gives a total of four new designs circuits. All the proposed decoders have compact transistor count compared to their conservative CMOS technologies. Finally, a variety of proposed designs present a noteworthy improvement in operating power and propagation delay, outperforming CMOS in almost all the cases.

An Area and Energy Efficient RAM Cell Design in Quantum Dot Cellular Automata

2019 ◽  
Vol 16 (10) ◽  
pp. 4179-4187
Author(s):  
Amanpreet Sandhu ◽  
Sheifali Gupta
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Quantum Dot Cellular Automata ◽  
Channel Effects

The Conventional Complementary Metal oxide semiconductor (CMOS) technology has been revolutionized from the past few decades. However, the CMOS circuit faces serious constraints like short channel effects, quantum effects, doping fluctuations at the nanoscale which limits them to further scaling down at nano meter range. Among various existing nanotechnologies, Quantum dot Cellular Automata (QCA) provides new solution at nanocircuit design. The technical advancement of the paper lies in designing a high performance RAM cell with less QCA cells, less occupational area and lower power dissipation characteristics. The design occupies 12.5% lower area, 16.6% lower input to output delay, and dissipates 18.26% lesser energy than the designs in the literature. The proposed RAMcell is robust due to lesser noise variations. Also it has less fabrication cost due to absence of rotated cells.

scholarly journals Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 477 ◽  
Author(s):  
Mohammad Arif Sobhan Bhuiyan ◽  
Md Torikul Islam Badal ◽  
Mamun Bin Ibne Reaz ◽  
Maria Liz Crespo ◽  
Andres Cicuttin
Keyword(s):  
Output Power ◽  
High Performance ◽  
High Efficiency ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Hot Electron ◽  
Oxide Breakdown ◽  
Rf Signals ◽  
Hot Electron Effect

Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the transmitter to propagate the required distance to the receiver. Attempted advancements of PA have focused on attaining high-performance RF signals for transmitters. Such PAs are expected to require low power consumption while producing a relatively high output power with a high efficiency. However, current PA designs in nanometer and micrometer complementary metal–oxide semiconductor (CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect. A well-defined architecture, including a linear and simple functional block synthesis, is critical in designing CMOS PA for various applications. This article describes the different state-of-the art design architectures of CMOS PA, including their circuit operations, and analyzes the performance of PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications.

scholarly journals High Performance Seesaw Torsional CMOS-MEMS Relay Using Tungsten VIA Layer

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 579 ◽  
Author(s):  
Martín Riverola ◽  
Francesc Torres ◽  
Arantxa Uranga ◽  
Núria Barniol
Keyword(s):  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Life Time ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Mechanical Contact ◽  
Contact Materials ◽  
Monolithically Integrated ◽  
Cmos Mems ◽  
Mechanical Logic

In this paper, a seesaw torsional relay monolithically integrated in a standard 0.35 μm complementary metal oxide semiconductor (CMOS) technology is presented. The seesaw relay is fabricated using the Back-End-Of-Line (BEOL) layers available, specifically using the tungsten VIA3 layer of a 0.35 μm CMOS technology. Three different contact materials are studied to discriminate which is the most adequate as a mechanical relay. The robustness of the relay is proved, and its main characteristics as a relay for the three different contact interfaces are provided. The seesaw relay is capable of a double hysteretic switching cycle, providing compactness for mechanical logic processing. The low contact resistance achieved with the TiN/W mechanical contact with high cycling life time is competitive in comparison with the state-of-the art.

scholarly journals A Near-Infrared CMOS Silicon Avalanche Photodetector with Ultra-Low Temperature Coefficient of Breakdown Voltage

Micromachines ◽  
2021 ◽  
Vol 13 (1) ◽  
pp. 47
Author(s):  
Daoqun Liu ◽  
Tingting Li ◽  
Bo Tang ◽  
Peng Zhang ◽  
Wenwu Wang ◽  
...  
Keyword(s):  
Temperature Coefficient ◽  
Breakdown Voltage ◽  
High Performance ◽  
Near Infrared ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Infrared Light ◽  
Manufacturing Cost ◽  
Light Detection

Silicon avalanche photodetector (APD) plays a very important role in near-infrared light detection due to its linear controllable gain and attractive manufacturing cost. In this paper, a silicon APD with punch-through structure is designed and fabricated by standard 0.5 μm complementary metal oxide semiconductor (CMOS) technology. The proposed structure eliminates the requirements for wafer-thinning and the double-side metallization process by most commercial Si APD products. The fabricated device shows very low level dark current of several tens Picoamperes and ultra-high multiplication gain of ~4600 at near-infrared wavelength. The ultra-low extracted temperature coefficient of the breakdown voltage is 0.077 V/K. The high performance provides a promising solution for near-infrared weak light detection.

scholarly journals New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 368 ◽  
Author(s):  
Giulia Santoro ◽  
Giovanna Turvani ◽  
Mariagrazia Graziano
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Point Of View ◽  
Oxide Semiconductor ◽  
Strong Impact ◽  
Technological Advancement ◽  
Data Movement ◽  
Memory Wall

Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal–oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Computational study of the staircase molecular conductivity of polyoxovanadates adsorbed on Au(111)

2021 ◽  
Vol 50 (16) ◽  
pp. 5540-5551
Author(s):  
Almudena Notario-Estévez ◽  
Xavier López ◽  
Coen de Graaf
Keyword(s):  
Metal Oxide ◽  
Computational Study ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Molecular Conduction ◽  
Conduction Properties ◽  
Molecular Conductivity

This computational study presents the molecular conduction properties of polyoxovanadates V6O19 (Lindqvist-type) and V18O42, as possible successors of the materials currently in use in complementary metal–oxide semiconductor (CMOS) technology.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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