scholarly journals Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 477 ◽  
Author(s):  
Mohammad Arif Sobhan Bhuiyan ◽  
Md Torikul Islam Badal ◽  
Mamun Bin Ibne Reaz ◽  
Maria Liz Crespo ◽  
Andres Cicuttin
Keyword(s):  
Output Power ◽  
High Performance ◽  
High Efficiency ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Hot Electron ◽  
Oxide Breakdown ◽  
Rf Signals ◽  
Hot Electron Effect

Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the transmitter to propagate the required distance to the receiver. Attempted advancements of PA have focused on attaining high-performance RF signals for transmitters. Such PAs are expected to require low power consumption while producing a relatively high output power with a high efficiency. However, current PA designs in nanometer and micrometer complementary metal–oxide semiconductor (CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect. A well-defined architecture, including a linear and simple functional block synthesis, is critical in designing CMOS PA for various applications. This article describes the different state-of-the art design architectures of CMOS PA, including their circuit operations, and analyzes the performance of PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications.

Integrated Optoelectronic Devices on Silicon

2012 ◽  
Vol 1396 ◽  
Author(s):  
Di Liang ◽  
John E. Bowers
Keyword(s):  
Output Power ◽  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Continuous Wave ◽  
Light Emission ◽  
Extinction Ratio ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Pockels Effect

ABSTRACTSilicon (Si) has been the dominating material platform of microelectronics over half century. Continuous technological advances in circuit design and manufacturing enable complementary metal-oxide semiconductor (CMOS) chips with increasingly high integration complexity to be fabricated in an unprecedently scale and economical manner. Conventional Si-based planar lightwave circuits (PLCs) has benefited from advanced CMOS technology but only demonstrate passive functionalities in most circumstances due to poor light emission efficiency and weak major electro-optic effects (e.g., Pockels effect, the Kerr effect and the Franz–Keldysh effect) in Si. Recently, a new hybrid III-V-on-Si integration platform has been developed, aiming to bridge the gap between Si and III-V direct-bandgap materials for active Si photonic integrated circuit applications. Since then high-performance lasers, amplifiers, photodetectors and modulators, etc. have been demonstrated. Here we review the most recent progress on hybrid Si lasers and high-speed hybrid Si modulators. The former include distributed feedback (DFB) lasers showing over 10 mW output power and up to 85 oC continuous-wave (cw) operation, compact hybrid microring lasers with cw threshold less than 4 mA and over 3 mW output power, and 4-channel hybrid Si AWG lasers with channel space of 360 GHz. Recently fabricated traveling-wave electro-absorption modulators (EAMs) and Mach-Zehnder interferometer modulators (MZM) on this platform support 50 Gb/s and 40 Gb/s data transmission with over 10 dB extinction ratio, respectively.

scholarly journals Photodetection Characteristics of Gold Coated AFM Tips and n-Silicon Substrate nano-Schottky Interfaces

2019 ◽  
Vol 9 (1) ◽  
Author(s):  
Yawar Abbas ◽  
Ayman Rezk ◽  
Fatmah Alkindi ◽  
Irfan Saadat ◽  
Ammar Nayfeh ◽  
...  
Keyword(s):  
Low Cost ◽  
Tunneling Current ◽  
High Sensitivity ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Hot Electron ◽  
Semiconductor Interface ◽  
Afm Tips ◽  
Tip Radius

Abstract Silicon (Si)-based photodetectors are appealing candidates due to their low cost and compatibility with the complementary metal oxide semiconductor (CMOS) technology. The nanoscale devices based on Si can contribute efficiently in the field of photodetectors. In this report, we investigate the photodetection capability of nano-Schottky junctions using gold (Au) coated conductive atomic force microscope (C-AFM) tips, and highly cleaned n-Si substrate interface. The Au nanotip/n-Si interface forms the proposed structure of a nano Schottky diode based photodetector. The electrical characteristics measured at the nanoscale junction with different Au nanotip radii show that the tunneling current increases with decreasing the tip radius. Moreover, the tunneling process and photodetection effects are discussed in terms of barrier width/height decrease at the tip-semiconductor interface due to the applied electric field as well as the generation of plasmon-induced hot-electron at the nanoparticle (i.e. C-AFM tip)/n-Si interface. Furthermore, the photodetection sensitivity is investigated and it is found to be higher for C-AFM tips with smaller radii. Moreover, this research will open a new path for the miniaturization of photodetectors with high sensitivity based on nano-Schottky interfaces.

Easily Cascaded Memristor-CMOS Hybrid Circuit for High-Efficiency Boolean Logic Implementation

2018 ◽  
Vol 28 (12) ◽  
pp. 1850149 ◽  
Author(s):  
Zhekang Dong ◽  
Donglian Qi ◽  
Yufei He ◽  
Zhao Xu ◽  
Xiaofang Hu ◽  
...  
Keyword(s):  
High Efficiency ◽  
Operating Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Boolean Logic ◽  
Oxide Semiconductor ◽  
Total Delay ◽  
Switching Dynamics ◽  
Two Phases ◽  
Logic Operations

Memristor is a novel passive electronic element with resistance-switching dynamics. Due to the threshold property and the variable conductivity of the memristive element, its composite circuits are promising for the implementation of logic operations. In this paper, a flexible logic circuit based on the threshold-type memristor and the mature complementary metal-oxide-semiconductor (CMOS) technology is designed for the realization of Boolean logic operations. Specifically, the proposed method is able to perform the NAND, AND, OR, and NOR gate operations through two phases, i.e. the writing operation and the reading operation. In such implementation, the total delay is very small especially for time-sequence inputs. Furthermore, for existing memristor-based logic implementation, a contrastive analysis with relevant computer simulations is carried out. The experimental results indicate that the proposed method is capable of realizing all basic Boolean logic operations, and some more complicated cascaded logic operations with more compact circuit structures, higher efficiency, and lower operating cost.

A 60 GHz 14 dBm power amplifier with a transformer-based power combiner in 65 nm CMOS

2011 ◽  
Vol 3 (2) ◽  
pp. 99-105 ◽  
Author(s):  
Dixian Zhao ◽  
Ying He ◽  
Lianming Li ◽  
Dieter Joos ◽  
Wim Philibert ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Peak Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
60 Ghz ◽  
Power Combiner ◽  
Power Added Efficiency ◽  
Saturated Output Power

A 52–61 GHz power amplifier (PA) is implemented in 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The proposed PA employs a transformer-based power combiner to sum the output power from two unit PAs. Each unit PA uses transformer-coupled two-stage differential cascode topology. The differential cascode PA is able to increase the output power and ensure stability. The transformer-based passives enable a compact layout with the PA core area of only 0.3 mm2. The PA achieves a peak power gain of 10.2 dB with 3-dB bandwidth of 9 GHz. The measured saturated output power is 14.8 dBm with a peak power-added efficiency (PAE) of 7.2%. The reverse isolation is smaller than −33 dB from 25 to 65 GHz. The PA consumes a quiescent current of 143 mA from a 1.6 V supply.

scholarly journals Design and Implementation of High Performance and Low Power Mixed Logic Line Decoders

2019 ◽  
Vol 8 (6S4) ◽  
pp. 635-640
Keyword(s):  
High Performance ◽  
Data Transfer ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Analog To Digital ◽  
Delay Performance ◽  
And Performance ◽  
Almost All

The decoders are widely used in the logical circuits, data transfer circuits and analog to digital conversions. A mixed logic design methods for the line decoders are used to combining the transmission gate logic, pass transistor logic, and complementary metal-oxide semiconductor (CMOS) technology provides desired operation and performance. A novel topology is presented for the 2 to 4 decoder requires a fourteen transistor topology aiming on reducing the transistor count and operating power and a fifteen transistor topology aiming on high power and low delay performance. The standard and inverting decoders are designed in each of the case, gives a total of four new designs circuits. All the proposed decoders have compact transistor count compared to their conservative CMOS technologies. Finally, a variety of proposed designs present a noteworthy improvement in operating power and propagation delay, outperforming CMOS in almost all the cases.

An Area and Energy Efficient RAM Cell Design in Quantum Dot Cellular Automata

2019 ◽  
Vol 16 (10) ◽  
pp. 4179-4187
Author(s):  
Amanpreet Sandhu ◽  
Sheifali Gupta
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Quantum Dot Cellular Automata ◽  
Channel Effects

The Conventional Complementary Metal oxide semiconductor (CMOS) technology has been revolutionized from the past few decades. However, the CMOS circuit faces serious constraints like short channel effects, quantum effects, doping fluctuations at the nanoscale which limits them to further scaling down at nano meter range. Among various existing nanotechnologies, Quantum dot Cellular Automata (QCA) provides new solution at nanocircuit design. The technical advancement of the paper lies in designing a high performance RAM cell with less QCA cells, less occupational area and lower power dissipation characteristics. The design occupies 12.5% lower area, 16.6% lower input to output delay, and dissipates 18.26% lesser energy than the designs in the literature. The proposed RAMcell is robust due to lesser noise variations. Also it has less fabrication cost due to absence of rotated cells.

scholarly journals High Performance Seesaw Torsional CMOS-MEMS Relay Using Tungsten VIA Layer

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 579 ◽  
Author(s):  
Martín Riverola ◽  
Francesc Torres ◽  
Arantxa Uranga ◽  
Núria Barniol
Keyword(s):  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Life Time ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Mechanical Contact ◽  
Contact Materials ◽  
Monolithically Integrated ◽  
Cmos Mems ◽  
Mechanical Logic

In this paper, a seesaw torsional relay monolithically integrated in a standard 0.35 μm complementary metal oxide semiconductor (CMOS) technology is presented. The seesaw relay is fabricated using the Back-End-Of-Line (BEOL) layers available, specifically using the tungsten VIA3 layer of a 0.35 μm CMOS technology. Three different contact materials are studied to discriminate which is the most adequate as a mechanical relay. The robustness of the relay is proved, and its main characteristics as a relay for the three different contact interfaces are provided. The seesaw relay is capable of a double hysteretic switching cycle, providing compactness for mechanical logic processing. The low contact resistance achieved with the TiN/W mechanical contact with high cycling life time is competitive in comparison with the state-of-the art.

scholarly journals A Near-Infrared CMOS Silicon Avalanche Photodetector with Ultra-Low Temperature Coefficient of Breakdown Voltage

Micromachines ◽  
2021 ◽  
Vol 13 (1) ◽  
pp. 47
Author(s):  
Daoqun Liu ◽  
Tingting Li ◽  
Bo Tang ◽  
Peng Zhang ◽  
Wenwu Wang ◽  
...  
Keyword(s):  
Temperature Coefficient ◽  
Breakdown Voltage ◽  
High Performance ◽  
Near Infrared ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Infrared Light ◽  
Manufacturing Cost ◽  
Light Detection

Silicon avalanche photodetector (APD) plays a very important role in near-infrared light detection due to its linear controllable gain and attractive manufacturing cost. In this paper, a silicon APD with punch-through structure is designed and fabricated by standard 0.5 μm complementary metal oxide semiconductor (CMOS) technology. The proposed structure eliminates the requirements for wafer-thinning and the double-side metallization process by most commercial Si APD products. The fabricated device shows very low level dark current of several tens Picoamperes and ultra-high multiplication gain of ~4600 at near-infrared wavelength. The ultra-low extracted temperature coefficient of the breakdown voltage is 0.077 V/K. The high performance provides a promising solution for near-infrared weak light detection.

scholarly journals New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 368 ◽  
Author(s):  
Giulia Santoro ◽  
Giovanna Turvani ◽  
Mariagrazia Graziano
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Point Of View ◽  
Oxide Semiconductor ◽  
Strong Impact ◽  
Technological Advancement ◽  
Data Movement ◽  
Memory Wall

Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal–oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.

scholarly journals Cu Pillar Bump Development for 7-nm Chip Package Interaction (CPI) Technology

2020 ◽  
Vol 17 (1) ◽  
pp. 1-8
Author(s):  
Lei Fu ◽  
Milind Bhagavat ◽  
Cheryl Selvanayagam ◽  
Ken Leong ◽  
Ivor Barber
Keyword(s):  
Coming Out ◽  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Development Program ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Power Performance ◽  
Cu Pillar ◽  
Solder Bumps

Abstract Power, performance, and area gains are important metrics driving the complementary metal–oxide–semiconductor (CMOS) technology from older nodes to newer ones. Over past several decades, a steady downscaling of feature sizes of CMOS technology has been a leading force enabling continual improvement in circuit speeds and cost per functionality. Increase in functionality drives larger number of inputs/outputs (I/Os), and the scaling-driven small intellectual property (IP) block sizes force these larger number of I/Os to be accommodated by reduction of I/O pitches. The result is an unrelenting pressure to reduce bump pitches from one generation of CMOS to another. In contrast to 14-nm/16-nm nodes which used 150-um bump pitch coming out of a die, for 7-nm node, the industry is targeting 130-um bump pitch for high performance devices. With this pitch reduction, conventional tin/silver (SnAg) solder bumps face limitations in terms of bridging. Cu pillar bumps are the best candidate for smaller bump pitches. However, for large die sizes prevalent in high-performance computing (HPC), the Cu pillar bumps will induce higher stress on the silicon resulting in higher risks of extremely low K (ELK) cracking. If copper pillar bumps are not properly developed, then there is a risk of marginal reliability in terms of chip package interaction. The situation becomes even more dire in large die sizes, where coefficient of thermal expansion mismatch between silicon and laminate substrate magnifies the stress. The present article discusses successful development of Cu pillar bumps for 7-nm technology. The development program included a 2-step development path. In the first step, extensive thermomechanical modeling was carried out to find optimal design of copper pillar bump for robustness of interactions with 7-nm back end of line ELK layers. In the second step, a 460-mm2 7-nm Silicon test vehicle was fabricated, and its assembly process was optimized to characterize the copper pillar bumps and prove their extended reliability on 7-nm silicon. As a result of this development, copper pillar technology has been qualified on Advanced Micro Devices (AMD) products. Today, copper pillar is a fully integral part of AMD's ever-growing 7-nm product offering in HPC.

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