scholarly journals A Highly Linear Low-Noise Transimpedance Amplifier for Indoor Fiber-Wireless Remote Antenna Units

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 437 ◽  
Author(s):  
Guillermo Royo ◽  
Antonio D. Martinez-Perez ◽  
Carlos Sanchez-Azqueta ◽  
Concepcion Aldea ◽  
Santiago Celma
Keyword(s):  
Cmos Technology ◽  
Antenna System ◽  
Open Loop ◽  
Low Noise ◽  
Total Power ◽  
Transimpedance Amplifier ◽  
Optimized Design ◽  
Error Vector Magnitude ◽  
Digitally Programmable ◽  
Total Power Consumption

This article presents an optimized design of a low-noise transimpedance amplifier (TIA) with high linearity for use in the downlink receiver of a remote antenna unit (RAU). The aim of this design is to be used in a cost-effective indoor distributed antenna system (DAS) for WLAN transmission using a mixed fiber-wireless system. The circuit topology consists of a fully differential shunt–shunt feedback TIA with digitally programmable transimpedance. An open-loop gain compensation technique is used to maintain stability and constant bandwidth (BW). The TIA has been fabricated in 65 nm CMOS technology with a 1.2 V voltage supply. The total power consumption of the TIA is 6 mW. A complete electrical and optical characterization with a 1550 nm PIN photodiode has been performed to demonstrate the reliable 54 Mb/s 802.11a WLAN transmission achieved with an error vector magnitude (EVM) lower than 3% for a 20 dB optical input range.

scholarly journals CURRENT REUSE ACTIVE INDUCTOR BASED WIDEBAND LNA

2013 ◽  
pp. 1-7
Author(s):  
DIPALI DASH ◽  
MARINA E J ◽  
J MANJULA
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
Critical Role ◽  
Cmos Technology ◽  
Low Noise ◽  
Total Power ◽  
Active Inductor ◽  
Main Function ◽  
Current Reuse ◽  
Total Power Consumption

This paper presents the design of an active inductor based wideband LNA using current reuse topology,which is designed and simulated in 0.18um CMOS technology. The low noise amplifier is considered to be the key block in an RF receiver. It plays a critical role in determining the noise figure of a receiver. The main function of an LNA is to provide sufficient gain to reduce the noise of subsequent stages while adding as little noise as possible. To achieve a good impedance matching over a desire bandwidth (0.05GHz to1.5GHz) active inductor is implemented based on gyrator structure and its noise is improved by employing a feed-forward path (FFP). The simulations show a maximum power gain of 17.32dB, minimum noise figure (NF) of 0.87dB with a 3db bandwidth of 1.0GHz over 0.05-1.5 GHz range. The total power consumption is 6.38mW with 1.8V power supply.

scholarly journals Design an Improved Structure for 10-Bit Pipeline Analog to Digital Converter Based on 0.18µm CMOS Technology

2019 ◽  
Vol 9 (2) ◽  
pp. 169-176
Author(s):  
Arash Rezapour ◽  
Farbod Setoudeh ◽  
Mohammad Bagher Tavakoli
Keyword(s):  
Data Transfer ◽  
Input Voltage ◽  
Cmos Technology ◽  
Open Loop ◽  
Total Power ◽  
Analog To Digital ◽  
Second Stage ◽  
Novel Structure ◽  
Total Power Consumption ◽  
Two Stages

Abstract This paper proposed a novel structure of a 10-bit, 400MS/s pipelined analog to digital convertor using 0.18 µm TSMC technology. In this paper, two stages are used to converter design and a new method is proposed to increase the speed of the pipeline analog to digital convertor. For this purpose, the amplifier is not used at the first stage and the buffer is used for data transfer to the second stage, in the second stage an amplifier circuit with accurate gain of 8 that is open loop with a new structure was used to speed up, also the design is such that the first 4 bits are extracted simultaneously with sampling. On the other hand, in this structure, since in the first stage the information is not amplified and transferred to the second stage, the accuracy of the comparator circuit should be high, therefore a new structure is proposed to design a comparator circuit that can detect unwanted offsets and eliminate them without delay, and thus can detect the smallest differences in input voltage. The proposed analog to digital convertor was designed with a resolution of 10 bits and a speed of 400MS/s, with the total power consumption 74.3mW using power supply of 1.8v.

scholarly journals A Tunable-Gain Transimpedance Amplifier for CMOS-MEMS Resonators Characterization

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 82
Author(s):  
Rafel Perelló-Roig ◽  
Jaume Verd ◽  
Sebastià Bota ◽  
Jaume Segura
Keyword(s):  
Cmos Technology ◽  
Open Loop ◽  
Transimpedance Amplifier ◽  
Mems Devices ◽  
Monolithically Integrated ◽  
Mems Resonators ◽  
Electromechanical Performance ◽  
Cmos Mems ◽  
Promising Solution ◽  
On Chip

CMOS-MEMS resonators have become a promising solution thanks to their miniaturization and on-chip integration capabilities. However, using a CMOS technology to fabricate microelectromechanical system (MEMS) devices limits the electromechanical performance otherwise achieved by specific technologies, requiring a challenging readout circuitry. This paper presents a transimpedance amplifier (TIA) fabricated using a commercial 0.35-µm CMOS technology specifically oriented to drive and sense monolithically integrated CMOS-MEMS resonators up to 50 MHz with a tunable transimpedance gain ranging from 112 dB to 121 dB. The output voltage noise is as low as 225 nV/Hz1/2—input-referred current noise of 192 fA/Hz1/2—at 10 MHz, and the power consumption is kept below 1-mW. In addition, the TIA amplifier exhibits an open-loop gain independent of the parasitic input capacitance—mostly associated with the MEMS layout—representing an advantage in MEMS testing compared to other alternatives such as Pierce oscillator schemes. The work presented includes the characterization of three types of MEMS resonators that have been fabricated and experimentally characterized both in open-loop and self-sustained configurations using the integrated TIA amplifier. The experimental characterization includes an accurate extraction of the electromechanical parameters for the three fabricated structures that enables an accurate MEMS-CMOS circuitry co-design.

scholarly journals ANALYSIS AND DESIGN OF A NEW STRUCTURE FOR 10-BIT 350MS/S PIPELINE ANALOG TO DIGITAL CONVERTER

2019 ◽  
Vol 8 (3) ◽  
Author(s):  
Arash Rezapour ◽  
Mohammad Bagher Tavakoli ◽  
Farbod Setoudeh
Keyword(s):  
Power Supply ◽  
Data Transfer ◽  
Open Loop ◽  
Total Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Analysis And Design ◽  
Second Stage ◽  
Total Power Consumption

A 10-bit pipelined Analog to Digital converter is proposed in this paper with using 0.18 µm TSMC technology. In this paper, a new structure is proposed to increase the speed of the pipeline analog to digital convertor. So at the first stage is not used the amplifier and instead the buffer is used for data transfer to the second stage. The speed of this converter is 350MS/s. An amplifier circuit with accurate gain of 6 and a very accurate unit gain buffer circuit that are open loop with a new structure were. used. In this Converter, the first 3 bits are extracted simultaneously with sampling. The proposed analog-to-digital converter was designed with the total power consumption 75mW using power supply of 1.8v.

High Gain and Low Noise Single Balanced Wireless Receiver Front-End Circuit Design

2013 ◽  
Vol 284-287 ◽  
pp. 2647-2651
Author(s):  
Zhe Yang Huang ◽  
Che Cheng Huang ◽  
Jung Mao Lin ◽  
Chung Chih Hung
Keyword(s):  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Chip Area ◽  
Wireless Receiver ◽  
Front End ◽  
Total Power Consumption

This paper presents a wideband wireless receiver front-end for 3.1-5.0GHz band group-1 (BG-1) WiMedia application. The front-end circuits are designed in 0.18um standard CMOS process. The experimental results show the maximum conversion power gain is 45.5dB; minimum noise figure is 2.9dB. Input return loss is lower than -9.3dB and output return loss is lower than -6.8dB. The maximum LO conversion power is 0dBm. 3dB working frequency is 1.9GHz (3.1GHz-5.0GHz) Total power consumption is 24.3mW including LNA, mixer and all buffers. Total chip area is 1.27mm2 including dummy and pads.

scholarly journals Noise-Cancelling CMOS Active Inductor and Its Application in RF Band-Pass Filter Design

2010 ◽  
Vol 2010 ◽  
pp. 1-8 ◽  
Author(s):  
Santosh Vema Krishnamurthy ◽  
Kamal El-Sankary ◽  
Ezz El-Masry
Keyword(s):  
Filter Design ◽  
Low Noise ◽  
Total Power ◽  
Active Inductor ◽  
Cmos Process ◽  
Band Pass Filter ◽  
Pass Filter ◽  
Noise Cancelling ◽  
Total Power Consumption ◽  
Band Pass

A CMOS active inductor with thermal noise cancelling is proposed. The noise of the transistor in the feed-forward stage of the proposed architecture is cancelled by using a feedback stage with a degeneration resistor to reduce the noise contribution to the input. Simulation results using 90 nm CMOS process show that noise reduction by 80% has been achieved. The maximum resonant frequency and the quality factor obtained are 3.8 GHz and 405, respectively. An RF band-pass filter has been designed based on the proposed noise cancelling active inductor. Tuned at 3.46 GHz, the filter features total power consumption of 1.4 mW, low noise figure of 5 dB, and IIP3 of −10.29 dBm.

scholarly journals A Novel General Purpose Combined DFVF/VCII Based Biomedical Amplifier

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 331
Author(s):  
Vincenzo Stornelli ◽  
Gianluca Barile ◽  
Alfiero Leoni
Keyword(s):  
Input Impedance ◽  
Cutoff Frequency ◽  
Circuit Complexity ◽  
Low Noise ◽  
Total Power ◽  
High Input ◽  
High Input Impedance ◽  
Sensing Applications ◽  
Wide Range ◽  
Total Power Consumption

We here present a 0.15 µm CMOS high input impedance and low noise AC coupled flipped voltage follower-based amplifier for high integration level in integrated circuits in a wide range of sensing applications. With such a circuit, it is possible to achieve a high level of integration, thanks to the absence of passive resistors, and also to implement a very high input impedance without capacitive feedback thanks to bootstrap operation, thus offering a very low high-pass cutoff frequency. Simulated results with a proven and well modeled standard technology show a whole circuit input-referred noise of 5.4 µVrms. The bias voltage is ±0.6 V with a total power consumption of the single amplifier of 20 µW. The very low circuit complexity allows a very low estimated reduced area occupation giving, as a general example, the possibility of integrating an array of up to thousands of channels for biomedical applications. Detailed simulation results, PVT analysis and comparison tables are also presented in the paper.

scholarly journals 60 GHz Front-End Components for Broadband Wireless Communication in 130 nm CMOS Technology

2016 ◽  
Vol 21 (1) ◽  
pp. 67-77
Author(s):  
Vasilis Kolios ◽  
Konstantinos Giannakidis ◽  
Grigorios Kalivas
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Spectral Space ◽  
60 Ghz ◽  
Front End ◽  
Total Power Consumption ◽  
5 Ghz

Abstract The over 5 GHz available spectral space allocated worldwide around the 60 GHz band, is very promising for very high data rate wireless short-range communications. In this article we present two key components for the 60 GHz front-end of a transceiver, in 130 nm RF CMOS technology: a single-balanced mixer with high Conversion Gain (CG), reduced Noise Figure (NF) and low power consumption, and an LC cross-coupled Voltage Controlled Oscillator (VCO) with very good linearity, with respect to Vctrl, and very low Phase Noise (PN). In both circuits, custom designed inductors and a balun structure for the mixer are employed, in order to enhance their performance. The VCO’s inductor achieves an inductance of 198 pH and a quality factor (Q) of 30, at 30 GHz. The balun shows less than 1o Phase Imbalance (PI) and less than 0.2 dB Amplitude Imbalance (AI), from 57 to 66 GHz. The mixer shows a CG greater than 15 dB and a NF lower than 12 dB. In addition, the VCO achieves a Phase Noise lower than -106 dBc/Hz at 1 MHz offset, and shows great linearity for the entire band. Both circuits are biased with a 1.2 V supply voltage and the total power consumption is about 10.6 mW for the mixer and 10.92 mW for the VCO.

scholarly journals Analysis and Design of Colpitts Oscillator for Short-range WSN

2016 ◽  
Vol 62 (3) ◽  
pp. 279-282
Author(s):  
Mousa Yousefi
Keyword(s):  
Energy Efficiency ◽  
Output Power ◽  
Short Range ◽  
Cmos Technology ◽  
Paper Analysis ◽  
Total Power ◽  
Colpitts Oscillator ◽  
Analysis And Design ◽  
Total Power Consumption ◽  
On Chip

Abstract In this paper, analysis and design of colpitts oscillator with ability to transmit data at low output power with application in short-range wireless sensor networks such as MICS is described. Reducing the area required to implement the transmitter, on-chip implementation and appropriate energy efficiency are the advantages of this structure that makes it suitable for the design of short-range transmitter in biomedical applications. The proposed OOK transmitter works at 405 MHz with 10 Mbps data rate. Output power and total power consumption are 25 µW and 726 µW, respectively. Energy efficiency is 72.6 pJ/bit. The transmitter has been designed and simulated in 0.18 µm CMOS technology.

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