scholarly journals Fabrication of Ceramic Interposers for Module Packaging

2020 ◽  
Vol 17 (2) ◽  
pp. 67-72
Author(s):  
Rana Alizadeh ◽  
Kaoru Uema Porter ◽  
Tom Cannon ◽  
Simon S. Ang
Keyword(s):  
Low Temperature ◽  
Fabrication Process ◽  
Electrical Insulation ◽  
Mechanical Support ◽  
Power Electronic ◽  
Power Semiconductor ◽  
Direct Bond ◽  
3D Printed ◽  
Direct Bond Copper

Abstract In this study, low-temperature cofired ceramic (LTCC) and 3D-printed ceramic interposers are designed and fabricated for a double-sided power electronic module. The interposer acts as electrical insulation between two direct-bond copper (DBC) power substrates as well as mechanical support to evenly distribute the weight of the top DBC substrate onto the entire bottom DBC substrate instead of directly onto the bare power semiconductor die. A novel LTCC fabrication process for 14 layers of green tapes with premachined recesses and holes is developed. A similar interposer is 3D printed using a ceramic resin. Finally, the fabricated LTCC and 3D-printed interposers are compared.

Design of a Low Inductance Power Module Based on Low Temperature Co-fired Ceramic

2016 ◽  
Vol 2016 (CICMT) ◽  
pp. 000032-000038
Author(s):  
Atanu Dutta ◽  
Simon S. Ang
Keyword(s):  
Low Temperature ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Devices ◽  
Building Blocks ◽  
Wide Bandgap ◽  
Switching Frequency ◽  
Full Potential ◽  
Power Electronic ◽  
Power Module ◽  
Parasitic Inductance

Abstract Efficient, compact, and reliable power electronic modules are building blocks of modern day power electronic systems. In recent times, wide bandgap semiconductor devices, such as, silicon carbide (SiC) and gallium nitride (GaN), are widely investigated and used in the power electronic modules to realize power dense, highly efficient, and fast switching modules for various applications. For high power applications is it required to parallel and series several devices to achieve high current and high voltage specifications, which results in larger current conducting traces. One of the major obstacles in using these wideband gap power semiconductor devices are the internal module stray inductance that is associated with these current conducting traces. With increasing demand for higher switching frequency, the internal module parasitic inductance must be reduced to as minimum as possible in order to utilize the full potential of the wide bandgap devices. A multi-layer approach of low-temperature co-fired ceramic (LTCC) to package the wide bandgap devices is investigated. The multi-layer design freedom by using LTCC can be utilized to reduce the footprint of the overall power module, electrical interconnects, hence, reducing the package parasitic inductance. LTCC also facilitates high temperature operations and has a coefficient of thermal expansion matching with wide bandgap devices. In this paper, we report on a LTCC based power module design where LTCC is utilized as an isolation layer between the source and the drain of the power devices. A simulation based parasitic inductance analysis and electro-thermal-mechanical study is performed using ANSYS Workbench Tools to investigate the feasibility of this LTCC based design.

A Robust, Composite Packaging Approach for a High Voltage 6.5kV IGBT and Series Diode

2015 ◽  
Vol 2015 (1) ◽  
pp. 000359-000364 ◽  
Author(s):  
Adam Morgan ◽  
Ankan De ◽  
Haotao Ke ◽  
Xin Zhao ◽  
Kasunaidu Vechalapu ◽  
...  
Keyword(s):  
High Voltage ◽  
Thermal Stresses ◽  
Wide Bandgap ◽  
Power Module ◽  
Cost Performance ◽  
Power Semiconductor ◽  
Current Switch ◽  
Power Modules ◽  
Voltage Stress ◽  
3D Printed

The main motivation of this work is to design, fabricate, test, and compare an alternative, robust packaging approach for a power semiconductor current switch. Packaging a high voltage power semiconductor current switch into a single power module, compared to using separate power modules, offers cost, performance, and reliability advantages. With the advent of Wide-Bandgap (WBG) semiconductors, such as Silicon-Carbide, singular power electronic devices, where a device is denoted as a single transistor or rectifier unit on a chip, can now operate beyond 10kV–15kV levels and switch at frequencies within the kHz range. The improved voltage blocking capability reduces the number of series connected devices within the circuit, but challenges power module designers to create packages capable of managing the electrical, mechanical, and thermal stresses produced during operation. The non-sinusoidal nature of this stress punctuated with extremely fast changes in voltage and current, with respect to time, leads to non-ideal electrical and thermal performance. An optimized power semiconductor series current switch is fabricated using an IGBT (6500V/25A die) and SiC JBS Diode (6000V/10A), packaged into a 3D printed housing, to create a composite series current switch package (CSCSP). The final chosen device configuration was simulated and verified in an ANSYS software package. Also, the thermal behavior of such a composite package was simulated and verified using COMSOL. The simulated results were then compared with empirically obtained data, in order to ensure that the thermal ratings of the power devices were not exceeded; directly affecting the maximum attainable frequency of operation for the CSCSP. Both power semiconductor series current switch designs are tested and characterized under hard switching conditions. Special attention is given to ensure the voltage stress across the devices is significantly reduced.

Low Temperature Direct Bond Technology for 3D Microelectronics Integration and Wafer Scale Packaging

2010 ◽  
Vol 2010 (1) ◽  
pp. 000015-000022
Author(s):  
Paul Enquist
Keyword(s):  
Low Temperature ◽  
Sensor Arrays ◽  
Cost Savings ◽  
Image Sensor ◽  
Network On Chip ◽  
Wafer Scale ◽  
Direct Bond ◽  
3D Network ◽  
On Chip ◽  
3D Volume

3D microelectronics integration and wafer scale packaging promise improvements in functional density and cost compared to conventional 2D microelectronics and packaging technologies. The realization of these improvements will require further adoption of 3D volume manufacturing process technologies. These process technologies will likely include through silicon via (TSV) and die or wafer bonding with and without 3D interconnect. Low temperature direct bond technologies have a number of inherent performance and cost advantages compared to other bonding technologies. This paper describes low temperature direct oxide bond technologies with and without a scalable 3D interconnect developed by Ziptronix and cost savings, performance and applications that will be enabled by adoption of these technologies. Enabled cost savings and performance include system or network-on-chip, system in package, and TSVs. Enabled applications include backside illuminated image sensors, micron-scale pitch vertically integrated image sensor arrays, 3D system-on-chip and 3D network-on-chip.

PREPARATION OF LOW TEMPERATURE RESISTANT AND HIGH ELECTRICAL INSULATION CHLOROPRENE RUBBER–BUTADIENE RUBBER BLENDS

2014 ◽  
Vol 87 (2) ◽  
pp. 360-369 ◽  
Author(s):  
Junping Zheng ◽  
Jin Tan ◽  
Hong Gao ◽  
Chuanzeng Wang ◽  
Zhilei Dong
Keyword(s):  
Mechanical Properties ◽  
Low Temperature ◽  
Mechanical Analysis ◽  
Electrical Insulation ◽  
Butadiene Rubber ◽  
Temperature Resistance ◽  
Rubber Blends ◽  
Chloroprene Rubber ◽  
Low Temperature Resistance ◽  
Electrical Insulation Properties

ABSTRACT To satisfy some special demands of many applications in the fields of aerospace and the electronic industry, low temperature resistant and high electrical insulation chloroprene rubber (CR) was prepared by blending pristine CR with different weight ratios of butadiene rubber (BR). The low temperature resistance, electrical insulation properties, and mechanical properties of CR/BR blends were investigated. With increasing BR content, the low temperature resistance and electrical insulation properties were improved, whereas the tensile strength and elongation at break decreased. For the CR/BR (65/35) blend, filled with SiO2, the brittleness temperature (Tb) was reduced to −61 °C and the high electrical insulation properties were obtained without sacrificing mechanical properties too much. The tan δ plots of CR/BR blends, investigated by dynamic mechanical analysis, also revealed that BR could reduce glass transition temperature (Tg) and improve low temperature resistance of CR. The phase contrast microscope images of CR/BR blends demonstrated that the phase structure of the blends changed with increasing BR content. Furthermore, the fracture surfaces of CR/BR blends, observed by scanning electron microscopy, showed that the compatibility of CR/BR blends was poor although the CR/BR blends were homogeneous in macrostructure.

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