Wafer-level packaging for ultra-thin glasses using hermetic room temperature welding technology

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 002203-002221 ◽  
Author(s):  
Heidi Lundén ◽  
Antti Peltonen ◽  
Antti Määttänen
Keyword(s):  
Heat Load ◽  
Adhesive Bonding ◽  
Wafer Level ◽  
Thin Glass ◽  
Wafer Level Packaging ◽  
Welding Technology ◽  
Direct Laser ◽  
Additive Materials ◽  
Manufacturing Technologies ◽  
Glass Packaging

The aim of the study was to develop a hermetic package using ultra-thin glass wafers. A novel glass welding technology, with a minimal heat load, was used to construct the encapsulations. Industry requirements of the miniaturization of the electronic components, for example in medical implants and consumer electronics and opto-electronics, challenge the conventional manufacturing technologies and package materials [1]. Low-cost glass interposers and packages have been research by GeorgiaTech at their PRC industry program. Glass packaging can offer even ten times affordable option than using silicon [2]. During the last few years, the advancements in the glass manufacturing technologies have enabled a cost effective production of the ultra-thin glass wafers and panels. Laborious glass grinding process from thick material to ultra-thin is no longer necessary since the fusion forming process can be used. Ultra-thin glass makes it possible to reduce the package size and weight [3]. Typically, glasses thickness of 300 μm or less are considered as ultra-thin material. However, even as thin as 25 μm glass is commercially available [4]. Several methods are used for glass joining including: anodic, fusion, and adhesive bonding [5]. During the recent years increasing number of laser based techniques are applied to glass packaging. Numerous studies have concentrated on frit bonding [6, 7]. Elementary study of the direct laser joining without any additive layers has been demonstrated by Miyamoto et al. [8]. Glass welding method has been further investigated in several researches [9, 10]. The package is constructed of three ultra-thin glass wafers: base and lid, thicknesses of 200 μm and spacer, thickness of 100 μm. Commercially available 6” borosilicate, D263T, wafers are used which were welded together by using novel laser welding technology. Welding is implemented on material interface without using any additive materials or coating layers. Glass surfaces are left untouched and optical quality is retained. Welding was performed on a wafer level and the single packages were cut after the final welding. Hermeticity test was performed to ensure the welding quality. Radioisotope leak test with krypton 85 was performed at Oneida Research Services. The results showed an excellent hermeticity: leak rate less than 6,0×10–12 atmcm3/s Kr-85 was achieved. Limits set in the MIL-standard are easily reached. The study proves that novel glass welding technology can be applied to wafer-level packaging with ultra-thin glasses. Technique eliminates the need of additive materials, and due to the minimal heat load bending and warping of the material can be avoided. Also, glass offers effortless visual inspection through the entire lifetime of the device.

Characterization of a Semiconductor Packaging System utilizing Through Glass Via (TGV) Technology

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001378-001407
Author(s):  
Tim Mobley ◽  
Roupen Keusseyan ◽  
Tim LeClair ◽  
Konstantin Yamnitskiy ◽  
Regi Nocon
Keyword(s):  
Low Cost ◽  
Glass Wafer ◽  
Wafer Level ◽  
Packaging System ◽  
Thin Glass ◽  
Wafer Level Packaging ◽  
Recent Developments ◽  
And Performance ◽  
New Generation ◽  
Semiconductor Packaging

Recent developments in hole formations in glass, metalizations in the holes, and glass to glass sealing are enabling a new generation of designs to achieve higher performance while leveraging a wafer level packaging approach for low cost packaging solutions. The need for optical transparency, smoother surfaces, hermetic vias, and a reliable platform for multiple semiconductors is growing in the areas of MEMS, Biometric Sensors, Medical, Life Sciences, and Micro Display packaging. This paper will discuss the types of glass suitable for packaging needs, hole creation methods and key specifications required for through glass vias (TGV's). Creating redistribution layers (RDL) or circuit layers on both sides of large thin glass wafer poses several challenges, which this paper will discuss, as well as, performance and reliability of the circuit layers on TGV wafers or substrates. Additionally, there are glass-to-glass welding techniques that can be utilized in conjunction with TGV wafers with RDL, which provide ambient glass-to-glass attachments of lids and standoffs, which do not outgas during thermal cycle and allow the semiconductor devices to be attached first without having to reflow at lower temperatures. Fabrication challenges, reliability testing results, and performance of this semiconductor packaging system will be discussed in this paper.

Damascene-Patterned Metal-Adhesive (Cu-BCB) Redistribution Layers

2006 ◽  
Vol 970 ◽  
Author(s):  
Ronald J. Gutmann ◽  
J. Jay McMahon ◽  
Jian-Qiang Lu
Keyword(s):  
Bonding Strength ◽  
Adhesive Bonding ◽  
Process Integration ◽  
Three Dimensional ◽  
Adhesive Layer ◽  
Wafer Level ◽  
Technology Platform ◽  
Metal Bonding ◽  
Wafer Level Packaging ◽  
Metal Metal

ABSTRACTA monolithic, wafer-level three-dimensional (3D) technology platform is described that is compatible with next-generation wafer level packaging (WLP) processes. The platform combines the advantages of both (1) high bonding strength and adaptability to IC wafer topography variations with spin-on dielectric adhesive bonding and (2) process integration and via-area advantages of metal-metal bonding. A copper-benzocyclobutene (Cu-BCB) process is described that incorporates single-level damascene-patterned Cu vias with partially-cured BCB as the bonding adhesive layer. A demonstration vehicle consisting of a two-wafer stack of 2-4 μm diameter vias has shown the bondability of both Cu-to-Cu and BCB-to-BCB. Planarization conditions to achieve BCB-BCB bonding with low-resistance Cu-Cu contacts have been examined, with wafer-scale planarization requirements compared to other 3D platforms. Concerns about stress induced at the tantalum (Ta) liner-to-BCB interface resulting in partial delamination are discussed. While across-wafer uniformity has not been demonstrated, the viability of this WLP-compatible 3D platform has been shown.

Wafer Level Package for MEMS with TSVs and Hermetic Seal

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002314-002335
Author(s):  
Akinori Shiraishi ◽  
Mitsutoshi Higashi ◽  
Kei Murayama ◽  
Yuichi Taguchi ◽  
Kenichi Mori
Keyword(s):  
Silicon Wafer ◽  
Adhesive Bonding ◽  
Anodic Bonding ◽  
Back Side ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Mems Device ◽  
Bonding Method ◽  
Wafer Level Package

In recent years, downsizing of MEMS package and high accuracy MEMS device mounting have been strongly required from expanding applications that using MEMS not only for industrial and automobile but also for consumer typified mobile phone. In order to achieve that, it is appropriate to use Silicon package that can be mounted at wafer level packaging. Silicon package is made of monocrystal silicon wafer. The deep cavity is fabricated on monocrystal silicon wafer by Wet or Dry etching. And MEMS device can be mounted on the cavity. The electrical connecting between front side and back side of cavity portion is achieved by TSVs that located on the bottom of cavity. Hermetic seal can be achieved by using glass or silicon wafer bonding method. By using a driver device wafer (before dicing) as the cap for hermetic seal, smaller size and smaller number of parts module can be fabricated. In this report, methods and designs for hermetic seal with wafer level process were examined. Methods that applied were polyimide adhesive bonding, anodic bonding and Au-In solder bonding. Location of TSVs on the bottom of cavity and thickness of diaphragm with TSVs was also examined. Silicon package for piezo type gyro MEMS that designed by the result of evaluation was fabricated. This package used optimized Au-In solder bonding for hermetic seal and optimized location of TSVs for interconnection. That was designed over 50% thinner than conventional ceramic packages. Characteristics of hermetic seal were evaluated by Q factor of gyro MEMS that mounted inside of the silicon package. It is confirmed that performance of sealing are good enough for running of the MEMS.

Thin Glass Handling Solutions for Microelectronics Packaging

2020 ◽  
Vol 2020 (1) ◽  
pp. 000192-000196
Author(s):  
Aric Shorey ◽  
Shelby Nelson ◽  
David Levy ◽  
Paul Ballentine
Keyword(s):  
Wafer Level ◽  
Microelectronics Packaging ◽  
Thin Glass ◽  
Glass Substrates ◽  
Wafer Level Packaging ◽  
Fine Pitch ◽  
Temporary Bonding ◽  
Bonding Technology ◽  
Rf Loss ◽  
Grinding Operations

Abstract Glass substrates with fine-pitch through-glass via (TGV) technology gives an attractive approach to wafer level packaging and systems integration. Glass can be made in very thin sheets (<100 um thick) which aids in integration and eliminates the need for back-grinding operations. Electrical and physical properties of glass have many attractive attributes such as low RF loss, the ability to adjust thermal expansion properties, and low roughness with excellent flatness to achieve fine L/S. Furthermore, glass can be fabricated in panel format to reduce manufacturing costs. The biggest challenge to adopting glass as a packaging substrate has been the existence of gaps in the supply chain, caused primarily by the difficulty in handling large, thin glass substrates using standard automation and processing equipment. This paper presents a temporary bonding technology that allows the thin glass substrates to be processed in a semiconductor fab environment without the need to modify existing equipment.

MEMS on LSI by Adhesive Bonding and Wafer Level Packaging

2012 ◽  
Vol 1427 ◽  
Author(s):  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Bonding ◽  
Communication Systems ◽  
Adhesive Bonding ◽  
Wireless Communication Systems ◽  
Surface Micromachining ◽  
Wafer Level ◽  
Open Collaboration ◽  
Wafer Level Packaging ◽  
Hands On ◽  
Mems Process

ABSTRACTResonators and switches are fabricated on LSI for advance wireless communication systems. In addition to surface micromachining, adhesive bonding has been applied for the fabrication. Lamb wave resonators are fabricated for multi-frequency oscillators by surface micromachining. Multi-band filters are formed by a MEMS process after bonding a Si wafer to a LSI wafer (wafer bonding first approach). SAW filters are made by bonding a MEMS wafer to a LSI wafer (wafer bonding last approach). Variable capacitors are fabricated on a piezoelectric LiNbO3 wafer. Wafer level packaging techniques are developed to encapsulate the MEMS on LSI. Open collaboration as shared wafer, prototyping facility and hands-on access fabrication facility are discussed to reduce a cost and a risk in the development of the MEMS on LSI.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

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