MEMS on LSI by Adhesive Bonding and Wafer Level Packaging

2012 ◽  
Vol 1427 ◽  
Author(s):  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Bonding ◽  
Communication Systems ◽  
Adhesive Bonding ◽  
Wireless Communication Systems ◽  
Surface Micromachining ◽  
Wafer Level ◽  
Open Collaboration ◽  
Wafer Level Packaging ◽  
Hands On ◽  
Mems Process

ABSTRACTResonators and switches are fabricated on LSI for advance wireless communication systems. In addition to surface micromachining, adhesive bonding has been applied for the fabrication. Lamb wave resonators are fabricated for multi-frequency oscillators by surface micromachining. Multi-band filters are formed by a MEMS process after bonding a Si wafer to a LSI wafer (wafer bonding first approach). SAW filters are made by bonding a MEMS wafer to a LSI wafer (wafer bonding last approach). Variable capacitors are fabricated on a piezoelectric LiNbO3 wafer. Wafer level packaging techniques are developed to encapsulate the MEMS on LSI. Open collaboration as shared wafer, prototyping facility and hands-on access fabrication facility are discussed to reduce a cost and a risk in the development of the MEMS on LSI.

Damascene-Patterned Metal-Adhesive (Cu-BCB) Redistribution Layers

2006 ◽  
Vol 970 ◽  
Author(s):  
Ronald J. Gutmann ◽  
J. Jay McMahon ◽  
Jian-Qiang Lu
Keyword(s):  
Bonding Strength ◽  
Adhesive Bonding ◽  
Process Integration ◽  
Three Dimensional ◽  
Adhesive Layer ◽  
Wafer Level ◽  
Technology Platform ◽  
Metal Bonding ◽  
Wafer Level Packaging ◽  
Metal Metal

ABSTRACTA monolithic, wafer-level three-dimensional (3D) technology platform is described that is compatible with next-generation wafer level packaging (WLP) processes. The platform combines the advantages of both (1) high bonding strength and adaptability to IC wafer topography variations with spin-on dielectric adhesive bonding and (2) process integration and via-area advantages of metal-metal bonding. A copper-benzocyclobutene (Cu-BCB) process is described that incorporates single-level damascene-patterned Cu vias with partially-cured BCB as the bonding adhesive layer. A demonstration vehicle consisting of a two-wafer stack of 2-4 μm diameter vias has shown the bondability of both Cu-to-Cu and BCB-to-BCB. Planarization conditions to achieve BCB-BCB bonding with low-resistance Cu-Cu contacts have been examined, with wafer-scale planarization requirements compared to other 3D platforms. Concerns about stress induced at the tantalum (Ta) liner-to-BCB interface resulting in partial delamination are discussed. While across-wafer uniformity has not been demonstrated, the viability of this WLP-compatible 3D platform has been shown.

Area-Selective Adhesive Bonding Using Photosensitive BCB for WL CSP Applications

2005 ◽  
Vol 127 (1) ◽  
pp. 7-11 ◽  
Author(s):  
A. Polyakov ◽  
M. Bartek ◽  
J. N. Burghartz
Keyword(s):  
Fracture Toughness ◽  
Tensile Strength ◽  
Wafer Bonding ◽  
Potential Application ◽  
Adhesive Bonding ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Rf Applications

This paper reports on an area-selective adhesive wafer bonding, using photosensitive BCB from Dow Co. The strength of the fabricated bonds is characterized using the wedge-opening and tensile methods. The measured fracture toughness is 53.5±3.9J/m2 with tensile strength up to 71 MPa. The potential application of BCB bonding is demonstrated on a concept of wafer-level chip-scale package for RF applications and microfilter array for microfluidic applications.

Metal Wafer Bonding for MEMS Applications

2008 ◽  
Vol 1139 ◽  
Author(s):  
Viorel Dragoi ◽  
Gerald Mittendorfer ◽  
Franz Murauer ◽  
Erkan Cakmak ◽  
Eric Pabo
Keyword(s):  
Intermetallic Compound ◽  
Eutectic Alloy ◽  
Wafer Bonding ◽  
Alloy Layer ◽  
Manufacturing Processes ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Metal Diffusion ◽  
Metal Layers ◽  
Different Levels

AbstractMetal layers can be used as bonding layers at wafer-level in MEMS manufacturing processes for device assembly as well as just for electrical integration of different levels. One has to distinguish between two main types of processes: metal diffusion bonding and bonding with formation of an interface eutectic alloy layer or an intermetallic compound. The different process principles determine also the applications area for each. From electrical interconnections to wafer-level packaging (with emphasis on vacuum packaging) metal wafer bonding is a very important technology in MEMS manufacturing processes.

Integrated Microsystems

2012 ◽  
Vol 81 ◽  
pp. 55-64 ◽  
Author(s):  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wireless Systems ◽  
Tactile Sensor ◽  
Wafer Level ◽  
Micro Electro Mechanical Systems ◽  
Silicon Chips ◽  
Open Collaboration ◽  
Wafer Level Packaging ◽  
Integrated Microsystems ◽  
Safety Systems ◽  
The Cost

Technology called MEMS (Micro Electro Mechanical Systems) or microsystems are heterogeneous integration on silicon chips and play important roles as sensors. MEMS as switches and resonators fabricated on LSI are needed for future multi-band wireless systems. MEMS for safety systems as event driven tactile sensor network for nursing robot are developed. Wafer level packaging for MEMS and open collaboration to reduce the cost for the development are discussed.

Patterned Permanent Bonding of Benzocyclobutene Based Dielectric Materials for Advanced Wafer Level Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000886-000912
Author(s):  
Jong-Uk Kim ◽  
Anupam Choubey ◽  
Rosemary Bell ◽  
Hua Dong ◽  
Michael Gallagher ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Dielectric Materials ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Integration Schemes ◽  
Device Reliability ◽  
Package Size ◽  
Microelectronics Industry ◽  
Improve Device ◽  
Joining Process

The microelectronics industry is being continually challenged to decrease package size, lower power consumption and improve device performance for the mobile communication and server markets. In order to keep pace with these requirements, device manufacturers and assembly companies are focused on developing 3D-TSV integration schemes that will require stacking of 50 um thinned wafers with gaps of 15 microns or less. While conventional underfill approaches have been demonstrated for chip to chip and chip to wafer schemes, new materials and processes are required for wafer to wafer bonding given the target bondline and wafer handling issues. Photopatternable, low temperature curable dielectrics offer a potential solution to solve the issues by eliminating the need for flow and material entrapment during the joining process. This should result in a simplified bonding process that enables wafer to wafer bonding with improved device reliability. In this work, we will focus on validating the critical steps including patterning and bonding that are required to demonstrate the utility of this process using an aqueous developable benzocyclobutene based photodielectric material.

Wafer Level Package for MEMS with TSVs and Hermetic Seal

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002314-002335
Author(s):  
Akinori Shiraishi ◽  
Mitsutoshi Higashi ◽  
Kei Murayama ◽  
Yuichi Taguchi ◽  
Kenichi Mori
Keyword(s):  
Silicon Wafer ◽  
Adhesive Bonding ◽  
Anodic Bonding ◽  
Back Side ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Mems Device ◽  
Bonding Method ◽  
Wafer Level Package

In recent years, downsizing of MEMS package and high accuracy MEMS device mounting have been strongly required from expanding applications that using MEMS not only for industrial and automobile but also for consumer typified mobile phone. In order to achieve that, it is appropriate to use Silicon package that can be mounted at wafer level packaging. Silicon package is made of monocrystal silicon wafer. The deep cavity is fabricated on monocrystal silicon wafer by Wet or Dry etching. And MEMS device can be mounted on the cavity. The electrical connecting between front side and back side of cavity portion is achieved by TSVs that located on the bottom of cavity. Hermetic seal can be achieved by using glass or silicon wafer bonding method. By using a driver device wafer (before dicing) as the cap for hermetic seal, smaller size and smaller number of parts module can be fabricated. In this report, methods and designs for hermetic seal with wafer level process were examined. Methods that applied were polyimide adhesive bonding, anodic bonding and Au-In solder bonding. Location of TSVs on the bottom of cavity and thickness of diaphragm with TSVs was also examined. Silicon package for piezo type gyro MEMS that designed by the result of evaluation was fabricated. This package used optimized Au-In solder bonding for hermetic seal and optimized location of TSVs for interconnection. That was designed over 50% thinner than conventional ceramic packages. Characteristics of hermetic seal were evaluated by Q factor of gyro MEMS that mounted inside of the silicon package. It is confirmed that performance of sealing are good enough for running of the MEMS.

Wafer Bonding Processes for the Manufacture of Microsystems

2008 ◽  
Author(s):  
Tony Rogers ◽  
Nick Aitken
Keyword(s):  
Bond Strength ◽  
Wafer Bonding ◽  
High Efficiency ◽  
Glass Frit ◽  
Acoustic Microscopy ◽  
Anodic Bonding ◽  
High Yield ◽  
Mems Devices ◽  
Wafer Level ◽  
Wafer Level Packaging

Wafer bonding is a widely used step in the manufacture of Microsystems, and serves several purposes: • Structural component of the MEMS device. • First level packaging. • Encapsulation of vacuum or controlled gas. In addition the technology is becoming more widely used in IC fabrication for wafer level packaging (WLP) and 3D integration. It is also widely used for the fabrication of micro fluidic structures and in the manufacture of high efficiency LED’s. Depending on the application, temperature constraints, material compatibility etc. different wafer bonding processes are available, each with their own benefits and drawbacks. This paper describes various wafer bonding processes that are applicable, not only to silicon, but other materials such as glass and quartz that are commonly used in MEMS devices. The process of selecting the most appropriate bonding process for the particular application is presented along with examples of anodic, glass frit, eutectic, direct, adhesive and thermo-compression bonding. The examples include appropriate metrology for bond strength and quality. The paper also addresses the benefits of being able to treat the wafer surfaces in-situ prior to bonding in order to improve yield and bond strength, and also discusses equipment requirements for achieving high yield wafer bonding, along with high precision alignment accuracy, good force and temperature uniformity, high wafer throughput, etc. Some common problems that can affect yield are identified and discussed. These include local temperature variations, that can occur with anodic bonding, and how to eliminate them; how to cope with materials of different thermal expansion coefficient; how best to deal with out-gassing and achieve vacuum encapsulation; and procedures for multi-stacking wafers of differing thicknesses. The presentation includes infra-red and scanning acoustic microscopy images of various bond types, plus some examples of what can go wrong if the correct manufacturing protocol is not maintained.

Evolution of Wafer Bonding Technology and Applications from Wafer-Level Packaging to Micro/Nanofluidics-Enhanced Sensing

2021 ◽  
pp. 187-215
Author(s):  
Jikai Xu ◽  
Zhihao Ren ◽  
Bowei Dong ◽  
Chenxi Wang ◽  
Yanhong Tian ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Bonding Technology
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