Innovated Process Integration for Panel Size Glass Substrate Manufacturing for SiP Application

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001893-001917 ◽  
Author(s):  
Yu-Hua Chen ◽  
Yu-Chung Hsieh ◽  
Wei-Di Lin ◽  
Chun-Hsien Chien ◽  
Dyi-Chung Hu
Keyword(s):  
Line Width ◽  
Glass Substrate ◽  
Process Integration ◽  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
Unit Cost ◽  
High Volume ◽  
Thin Glass ◽  
Panel Size ◽  
Wafer Processing

Although Silicon interposer has good performance, however high cost is still the major issue and limits its high volume adoption. Therefore to decrease the assembly cost or develop low cost, high density interconnect interposer technology is the keys to enable 2.5D SiP integration. One possibility is to develop low cost interposer by adopting the alternative materials instead of Silicon. The glass, low CTE polymer material, ceramic, etc. may be included. Glass represents an attractive choice with potential of tailorable properties dependent on specific glass composition. By targeting the coefficient of thermal expansion (CTE), the CTE of glass can be made to match perfectly with silicon dies and for reliable package. In addition, the advantages of using glass for interposer derive from process flexibility for size and thickness since the glass fusion process provides sheets with dimensions of more than three meters. It is straight forward to provide glass substrate of almost any size needed. Large glass panels are ideally suited for fabrication of interposer where the panel process is expected to provide large number of interposers in each run compared with wafer processing. Additionally, the two sided processing of the panel, the avoidance of Si wafer CMP processes further enable lower unit cost for the interposer Consequently, glass is an ideal interposer material due to its insulating property, large panel size availability, high modulus and ability to tailor CTE. In this paper, we successfully demonstrate manufacturing feasibility of glass substrate with 4 build-up layers starting with a thin glass panel in 508mm×508mm panel size format and under the IC substrate manufacturing environment. Glass thickness of 100~300um could be processed through the IC substrate HVM line. The laser via in via or direct metallization technology could be selected for double side electrical connection. The copper line width/space of 8/8um was demonstrated by current substrate HVM line. By adopting advanced lithography process and material, line width/space less than 2/2um was achievable. TCT Reliability test without glass crack results will also be discussed.

Development of Substrates for Through Glass Vias

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000832-000845 ◽  
Author(s):  
Aric Shorey ◽  
Scott Pollard
Keyword(s):  
Material Properties ◽  
Glass Composition ◽  
Coefficient Of Thermal Expansion ◽  
Cost Effective ◽  
High Volume ◽  
Chemical Durability ◽  
Thin Glass ◽  
Wide Range ◽  
Challenges And Opportunities ◽  
Substantial Progress

Through-substrate vias are critical for 3DS-IC integration. The choice of glass as an interposer substrate, TGV, present some interesting challenges and opportunities, making glass a compelling alternative to silicon. There are two primary challenges to begin building a precision interposer in thin glass. The first is high quality thin glass wafers (300 mm OD, thickness 0.05 to 0.10 mm, warp and TTV of 30 μm and 1 μm respectively). The second challenge is developing a process capable of providing small (5–10 μm) precision vias in a cost-effective way. “Glass” represents a large class of materials with a wide range of material properties. The first step in developing TGV is to identify the most appropriate glass composition for the application, which furthermore defines important properties such as coefficient of thermal expansion (CTE) and other mechanical properties, chemical durability and electrical properties. The manufacturing process used to develop the glass has a significant impact on quality and manufacturability. Fusion formed glass provides a solution for high volume manufacturing supply in an as-formed, ultra-thin, pristine glass manufactured to tight tolerances, and avoids the issues associated with polishing or thinning. The supply of 50 μm to 100 μm as-formed ultra-thin glass wafers can compare very favorably in cost relative to polished or thinned glass as well as thinned silicon wafer. While there are many technologies that have demonstrated vias in glass, challenges relating to via size and pitch, wafer strength and reliability remain to be resolved. However, substantial progress has been made to meet these challenges. Specific characterization data from some of these processes to demonstrate vias on the order of 10 μm diameter with a 100 μm glass thickness in alternative glass materials will be presented.

Low Cost Glass Interposer Development

2014 ◽  
Vol 2014 (1) ◽  
pp. 000397-000401 ◽  
Author(s):  
Yu-Hua Chen ◽  
Shaun Hsu ◽  
Urmi Ray ◽  
Ravi Shenoy ◽  
Kwan-Yu Lai ◽  
...  
Keyword(s):  
Low Cost ◽  
Organic Substrate ◽  
High Density ◽  
Organic Substrates ◽  
Test Vehicle ◽  
Thin Glass ◽  
Panel Size ◽  
Low Dielectric ◽  
Ic Packaging ◽  
Core Thickness

For high density interconnection IC packages of the future, the outlook is for thinner packages with higher routing densities. With that, managing the substrate warpage becomes critical. Traditional organic substrates may face several challenges for high density I/Os with very fine line interconnections. Glass is one of the candidates that can be used in substrate industry. The infrastructure of glass for LCD industry has already been developed for many years. Glass also has several superior properties than other substrate candidates, such as large panel size availability, adjustable CTE, high modulus, low dielectric constant, low dielectric loss and high insulating ability. In this paper, we successfully demonstrate early manufacturing feasibility of glass substrate with 4 build-up layers starting with a thin glass panel of thickness of 200μm in 508mm μ 508mm panel size format and under the IC substrate manufacturing environment. Fabrication and electrical results of a test vehicle are documented. The test vehicle includes daisy chains that are connected with 100μm diameter through glass via (TGV) in a 200μm thick glass. The laser via in via technology was adopted for double side electrical connection. The copper line width/space of 8/8μm was demonstrated. The total thickness of 4 layers test vehicle is about 390μm. The warpage of glass in comparison with an organic substrate (BT) with 200μm core thickness is 3X better. Further work is needed to develop, fine tune and assess the detailed manufacturability and reliability concerns. Based on this work, it is clear that the potential of glass in IC packaging and integration is tremendous in diverse applications for substrate warpage enhancement.

scholarly journals Large Area Graphene Deposition on Hydrophobic Surfaces, Flexible Textiles, Glass Fibers and 3D Structures

Coatings ◽  
2019 ◽  
Vol 9 (3) ◽  
pp. 183 ◽  
Author(s):  
Guobin Jia ◽  
Jonathan Plentz ◽  
Jan Dellith ◽  
Andrea Dellith ◽  
Ruri Wahyuono ◽  
...  
Keyword(s):  
Self Assembly ◽  
Glass Substrate ◽  
Large Scale ◽  
Low Cost ◽  
Glass Fibers ◽  
Flat Glass ◽  
Peel Test ◽  
Large Area ◽  
Thin Glass ◽  
Graphene Flakes

Graphene and its derivatives have many superior electrical, thermal, mechanical, chemical, and structural properties, and promise for many applications. One of the issues for scalable applications is the lack of a simple, reliable method that allows the deposit of a well-ordered monolayer using low-cost graphene flakes onto target substrates with different surface properties. Another issue is the adhesion of the deposited graphene thin film, which has not been well investigated yet. Following our former finding of a double self-assembly (DSA) process for efficient deposition of a monolayer of graphene flakes (MGFs), in this work we demonstrate that the DSA process can be applied even on very challenging samples including highly hydrophobic polytetrafluoroethylene (PTFE), flexible textiles, complex 3D objects, and thin glass fibers. Additionally, we tested adhesion of the graphene flakes on the flat glass substrate by scotch tape peel test of the MGFs. The results show that the graphene flakes adhere quite well on the flat glass substrate and most of the graphene flakes stay on the glass. These findings may trigger many large-scale applications of low-cost graphene feedstocks and other 2D materials.

A Novel Precision Die Attach Technique for Opto-Electronics Packaging

2011 ◽  
Author(s):  
V. Bhagavatula ◽  
S. Chaparala ◽  
J. Himmelreich
Keyword(s):  
Laser Diode ◽  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
Research Work ◽  
High Volume ◽  
Ceramic Substrates ◽  
Die Attach ◽  
Semiconductor Laser Diodes ◽  
The Cost ◽  
Low Cost Manufacturing

Semiconductor Laser diodes that emit visible light have various interesting applications such as sensing, high density optical storage and projection displays. In any opto-electronic package, the laser diode chips are typically attached or soldered to metal or ceramic substrates that have good thermal conductivity and are well-matched in coefficient of thermal expansion using solder. Some applications require a critical alignment of the front facet of the laser diode to the front edge of the substrate onto which the laser diode chip is attached to. Depending on the application, the alignment precision could be varying from 20 μm to being as stringent as 0.5 to 1 μm. In many of these applications, the cost of packaging is also a very important factor. In such applications, it is essential to develop a laser diode chip bonding process that can meet such stringent die alignments along with a low cost manufacturing process. Therefore, the objective of this research work is to provide a low cost alternative solution for die attach process that can guarantee alignment precision of 0.5 to 1 microns and can be easily adapted to high volume manufacturing. The novel technique proposed in this work uses primarily gravity force for the facet alignments between the two components. In this passive-gravity assisted precision (P-GAP) assembly process, the laser diode (LD) chip is placed on the substrate using a traditional pick and place machine and later the substrate and the chip are tilted such that the chip slides on the substrate due to the gravity and touches a mechanical stop in-front of them. This does not involve any active alignment. In addition, we have provided few ideas to improve the sliding when gravity is used. This technique has been implemented on several samples and the feasibility of achieving the alignment precision to within a micron was demonstrated.

scholarly journals A rapid, accurate, scalable, and portable testing system for COVID-19 diagnosis

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Guanhua Xun ◽  
Stephan Thomas Lane ◽  
Vassily Andrew Petrov ◽  
Brandon Elliott Pepa ◽  
Huimin Zhao
Keyword(s):  
Limit Of Detection ◽  
Low Cost ◽  
High Volume ◽  
N Gene ◽  
Testing System ◽  
Target Sequence ◽  
One Pot ◽  
Sequence Detection ◽  
Highly Sensitive ◽  
Speed Accuracy

AbstractThe need for rapid, accurate, and scalable testing systems for COVID-19 diagnosis is clear and urgent. Here, we report a rapid Scalable and Portable Testing (SPOT) system consisting of a rapid, highly sensitive, and accurate assay and a battery-powered portable device for COVID-19 diagnosis. The SPOT assay comprises a one-pot reverse transcriptase-loop-mediated isothermal amplification (RT-LAMP) followed by PfAgo-based target sequence detection. It is capable of detecting the N gene and E gene in a multiplexed reaction with the limit of detection (LoD) of 0.44 copies/μL and 1.09 copies/μL, respectively, in SARS-CoV-2 virus-spiked saliva samples within 30 min. Moreover, the SPOT system is used to analyze 104 clinical saliva samples and identified 28/30 (93.3% sensitivity) SARS-CoV-2 positive samples (100% sensitivity if LoD is considered) and 73/74 (98.6% specificity) SARS-CoV-2 negative samples. This combination of speed, accuracy, sensitivity, and portability will enable high-volume, low-cost access to areas in need of urgent COVID-19 testing capabilities.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

Mocvd SrS:Ce for Applications in Electroluminescent Devices

1997 ◽  
Vol 471 ◽  
Author(s):  
D. Endisch ◽  
K. Barth ◽  
J. Lau ◽  
G. Peterson ◽  
A. E. Kaloyeros ◽  
...  
Keyword(s):  
Process Development ◽  
Process Integration ◽  
Low Cost ◽  
Chemical Vapor ◽  
High Growth ◽  
Film Structure ◽  
High Growth Rate ◽  
Organic Chemical ◽  
Glass Substrates ◽  
Full Color

ABSTRACTSrS:Ce is an important material for full color electroluminescent (EL) flat panel displays. Using a combination of SrS:Ce/ZnS:Mn and appropriate color filters high quality full color displays have been demonstrated [1]. Major issues for commercially viable process integration of SrS:Ce are the combination of high luminance, high growth rate, and process temperatures below 600°C for compatibility with low cost glass substrates. This work describes the process development and optimization of metal-organic chemical vapor deposition (MOCVD) of SrS:Ce. MOCVD is a promising candidate for deposition of SrS:Ce because it can provide the required growth rates and allows control of crystal structure and stoichiometry. Growth of SrS:Ce was performed in the temperature range from 400°C to 530°C using Sr(tmhd)2, Ce(tmhd)4, and H2S as precursors. The structure of the SrS:Ce was found to be strongly dependent on the H2S flow. A brightness of 15 fL and an efficiency of 0.22 lm/W has been achieved (40 V above threshold voltage, 60 Hz AC). Film analysis included Rutherford backscattering (RBS), X-ray diffraction (XRD), atomic force microscopy (AFM), and EL measurements. Results on the correlation between process parameters, film structure, grain size and EL performance will be presented.

Plastic Encapsulated MCM Technology for High Volume, Low Cost Electronics

Circuit World ◽  
1995 ◽  
Vol 21 (2) ◽  
pp. 28-31 ◽  
Author(s):  
R. Fillion ◽  
R. Wojnarowski ◽  
T. Gorcyzca ◽  
E. Wildi ◽  
H. Cole
Keyword(s):  
Low Cost ◽  
High Volume

An Investigation onto Polydimethylsiloxane (PDMS) Printing Plate of Multiple Functional Solid Line by Flexographic

2013 ◽  
Vol 844 ◽  
pp. 158-161 ◽  
Author(s):  
M.I. Maksud ◽  
Mohd Sallehuddin Yusof ◽  
M. Mahadi Abdul Jamil
Keyword(s):  
Laser Ablation ◽  
Line Width ◽  
High Speed ◽  
Printed Electronics ◽  
Low Cost ◽  
Flexible Substrates ◽  
Large Area ◽  
Printing Plate ◽  
Roll To Roll ◽  
Printing Processes

Recently low cost production is vital to produce printed electronics by roll to roll manufacturing printing process like a flexographic. Flexographic has a high speed technique which commonly used for printing onto large area flexible substrates. However, the minimum feature sizes achieved with roll to roll printing processes, such as flexographic is in the range of fifty microns. The main contribution of this limitation is photopolymer flexographic plate unable to be produced finer micron range due to film that made by Laser Ablation Mask (LAMs) technology not sufficiently robust and consequently at micron ranges line will not be formed on the printing plate. Hence, polydimethylsiloxane (PDMS) is used instead of photopolymer. Printing trial had been conducted and multiple solid lines successfully printed for below fifty microns line width with no interference between two adjacent lines of the printed images.

scholarly journals Recovery of FTO coated glass substrate via environment-friendly facile recycling perovskite solar cells

RSC Advances ◽  
2021 ◽  
Vol 11 (24) ◽  
pp. 14534-14541
Author(s):  
M. S. Chowdhury ◽  
Kazi Sajedur Rahman ◽  
Vidhya Selvanathan ◽  
A. K. Mahmud Hasan ◽  
M. S. Jamal ◽  
...  
Keyword(s):  
Solar Cells ◽  
Glass Substrate ◽  
Large Scale ◽  
Low Cost ◽  
Perovskite Solar Cells ◽  
Potential Candidate ◽  
Photovoltaic Devices ◽  
Coated Glass Substrate ◽  
Environment Friendly ◽  
Coated Glass

Organic–inorganic perovskite solar cells (PSCs) have recently emerged as a potential candidate for large-scale and low-cost photovoltaic devices.

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