A CMOS SiC Linear Voltage Regulator for High Temperature Applications

2016 ◽  
Vol 2016 (HiTEC) ◽  
pp. 000106-000111 ◽  
Author(s):  
R.C. Murphree ◽  
S. Ahmed ◽  
M. Barlow ◽  
A. Rahman ◽  
H.A. Mantooth ◽  
...  
Keyword(s):  
Feedback Loop ◽  
Input Voltage ◽  
Voltage Regulator ◽  
Voltage Reference ◽  
Frequency Compensation ◽  
Error Amplifier ◽  
Linear Regulator ◽  
Load Regulation ◽  
Pass Transistor ◽  
Linear Voltage

Abstract This paper establishes the first linear regulator in a 1.2 μm CMOS silicon carbide (SiC) process. The linear regulator presented consists of a SiC error amplifier and a pass transistor which has a W/L = 70,000 μm / 1.2 μm. The feedback loop is internal and the frequency compensation network is a combination of internal and external components. As a result of potential process variation in this emerging technology, the voltage reference used at the negative input terminal of the error amplifier has been made external. With an input voltage of 20 V to 30 V, the voltage regulator is able to provide a 15 V output and a continuous load current of 100 mA at temperatures ranging from 25 °C to over 400 °C. At a temperature of 400 °C, testing of the fabricated circuit has shown line regulation of less than 4 mV/V. Under the same test conditions, a load regulation of less than 420 mV/A is achieved.

scholarly journals A Transient-Enhanced Voltage Regulator with Stability and Power-Supply-Rejection Boosting

2019 ◽  
Vol 14 (1) ◽  
Author(s):  
Yue Shi ◽  
Anqi Wang ◽  
Jianwen Cao ◽  
Zekun Zhou
Keyword(s):  
Power Supply ◽  
Low Voltage ◽  
Input Voltage ◽  
Voltage Regulator ◽  
Load Range ◽  
Load Regulation ◽  
The Stability ◽  
Output Capacitor ◽  
Better Than ◽  
Supply Rejection

AbstractA high-stability voltage regulator (VR) is proposed in this paper, which integrates transient enhancement and overcurrent protection (OCP). Taken into consideration the performance and area advantages of low-voltage devices, most control parts of proposed VR are supplied by the regulated output voltage, which forms self-power technique (SPT) with power supply rejection (PSR) boosting. Besides, the stability and transient response are enhanced by dynamic load technique (DLT). An embedded overcurrent feedback loop is also adopted to protect the presented VR from damage under overload situations. The proposed VR is implemented in a standard 350 nm BCD technology, whose results indicate the VR can steadily work with 5.5–30 V input voltage, 0–30 mA load range, and 0.1–3.3 μF output capacitor. A 2.98 μV/V line regulation and a 0.233 mV/mA load regulation are achieved with a 40 mA current limiting. The PSR is better than − 64 dB up to 10 MHz with a 0.1 μF output capacitor.

scholarly journals High-voltage circuits for power management on 65 nm CMOS

2015 ◽  
Vol 13 ◽  
pp. 109-120
Author(s):  
S. Pashmineh ◽  
D. Killat
Keyword(s):  
Power Management ◽  
Circuit Design ◽  
High Voltage ◽  
Cmos Technology ◽  
Buck Converter ◽  
Drop Out ◽  
Voltage Regulator ◽  
Error Amplifier ◽  
Load Regulation ◽  
Switching Characteristics

Abstract. This paper presents two high-voltage circuits used in power management, a switching driver for buck converter with optimized on-resistance and a low dropout (LDO) voltage regulator with 2-stacked pMOS pass devices. The circuit design is based on stacked MOSFETs, thus the circuits are technology independent. High-voltage drivers with stacked devices suffer from slow switching characteristics. In this paper, a new concept to adjust gate voltages of stacked transistors is introduced for reduction of on-resistance. According to the theory, a circuit is proposed that drives 2 stacked transistors of a driver. Simulation results show a reduction of the on-resistance between 27 and 86 % and a reduction of rise and fall times between 16 and 83 % with a load capacitance of 150 pF at various supply voltages, compared to previous work. The concept can be applied to each high-voltage driver that is based on a number (N) of stacked transistors. The high voltage compatibility of the low drop-out voltage regulator (LDO) is established by a 2-stacked pMOS transistors as pass device controlled by two regulators: an error amplifier and a 2nd amplifier adjusting the division of the voltages between the two pass transistors. A high GBW and good DC accuracy in line and load regulation is achieved by using 3-stage error amplifiers. To improve stability, two feedback loops are utilized. In this paper, the 2.5 V I/O transistors of the TSMC 65 nm CMOS technology are used for the circuit design.

BANDGAP VOLTAGE REFERENCE IC FOR HV AUTOMOTIVE APPLICATIONS WITH PSEUDO-REGULATED BIAS AND SERVICE REGULATOR

2013 ◽  
Vol 22 (01) ◽  
pp. 1250069 ◽  
Author(s):  
SERGIO SAPONARA ◽  
LUCA FANUCCI ◽  
TOMMASO BALDETTI ◽  
ENRICO PARDI
Keyword(s):  
Operating Temperature ◽  
Input Voltage ◽  
Automotive Application ◽  
Voltage Reference ◽  
Temperature Drift ◽  
Temperature Range ◽  
Linear Regulator ◽  
Bandgap Voltage Reference ◽  
Stable Voltage ◽  
Operating Temperature Range

The paper presents a bandgap voltage reference (BGR) implemented in TSMC 0.25 μm BCD technology for an automotive application. To withstand a car's battery large voltage variations, from 5 V to 40 V, the circuit features an embedded pseudo-regulator providing a stable bias current for the bandgap core. High-voltage (HV) MOS count has been kept low thus allowing the design of a compact BGR with an area of 0.118 mm2. The BGR has been designed to operate in automotive extended temperature range (-40°C to 150°C) and it provides a stable voltage of 1.21 V, which is also used as reference for a cascade 3.7 V linear regulator. Measurements carried on fabricated IC samples prove the effectiveness of the BGR design in terms of supported input voltage variations and operating temperature range, temperature drift, line regulation and PSRR performance.

scholarly journals A VERY LOW-DROPOUT VOLTAGE REGULATOR IN 0.18-M CMOS TECHNOLOGY FOR POWER MANAGEMENT SYSTEM

2020 ◽  
Vol 82 (6) ◽  
pp. 11-19
Author(s):  
Sohiful Anuar Zainol Murad ◽  
Azizi Harun ◽  
Mohd Nazrin Md Isa ◽  
Saiful Nizam Mohyar ◽  
Jamilah Karim
Keyword(s):  
Power Management ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Voltage Regulator ◽  
Voltage Reference ◽  
Error Amplifier ◽  
Transconductance Amplifier ◽  
Output Capacitor ◽  
Ldo Regulator ◽  
Pmos Transistor

This paper proposes the design of a very low-dropout (LDO) voltage regulator in 0.18-mm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results show that the proposed LDO is capable to operate from a supply voltage of 1.7-2.0 V with a low dropout voltage of 19.3 mV at a maximum 50 mA load current to regulate output voltage 1.5 V. The active chip is 2.96 mm2 in size. The performance of the proposed LDO is suitable to enhance power management for system on chip (SoC) applications.  

scholarly journals An RFID-Based Self-Biased 40 nm Low Power LDO Regulator for IoT Applications

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 396
Author(s):  
Asghar Bahramali ◽  
Marisa Lopez-Vallejo
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Maximum Load ◽  
The Elderly ◽  
Input Voltage ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Linear Regulator ◽  
The Disabled ◽  
Ldo Regulator

There are emerging applications, like bridge structural health monitoring, continuous patient condition and outdoor aiding of the elderly and the disabled, where Internet of things (IoT) nodes are used with very limited accessibility and no connection to the main supply network. They may also be exposed to harsh environmental conditions. These are applications where power and available area constraints are of great concern. In this paper, we design a 1.1 V low dropout (LDO) linear regulator in 40 nm technology to be embedded in IoT nodes. To address these constraints, we used state-of-the-art, variability-aware resistor-less sub-threshold biased CMOS-only ultra low power consumption configurations having low active area. The proposed LDO is internally compensated with embedded 18 pF Miller and 10 pF load capacitances. It can supply 1 mA maximum load current with 0.8 uA quiescent current. The dropout voltage of the regulator is 200 mV with minimum input voltage of 1.3 V. The efficiency of the regulator is 84%, which is about 99% of the maximum achievable efficiency for a 200 mV dropout voltage. The whole circuit, consisting of the embedded voltage reference and the Miller and load capacitances, takes less than 0.007 mm2 of the die size with 1 μW power consumption.

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