ARM Dual Core Product Demonstration with 2.5D Through-Silicon-Via (TSV)

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000665-000693
Author(s):  
Michael Kelly ◽  
Rick Reed
Keyword(s):  
High Speed ◽  
High Performance ◽  
Functional System ◽  
Process Technology ◽  
Test Vehicle ◽  
Through Silicon Via ◽  
The Real Estate ◽  
Key Factor ◽  
And Performance ◽  
Dual Core

Through-silicon-via (TSV) package construction offers several silicon integration advantages that are being validated by leading technology providers. This paper will describe a System in Package (SiP) design utilizing two functional system-on-chip (SoC) ARM dual-core Cortex-A9 processors connected across a 2.5D silicon interposer. The test vehicle was designed to demonstrate high speed and high bandwidth communication between multiple chips. The two logic chips were designed by Open Silicon, Inc. and fabricated by GLOBALFOUNDRIES on their 28nm-SLP (Super Low Power) process technology. GLOBALFOUNDRIES also fabricated the 2.5D interposer using their 65nm manufacturing flow. Amkor Technology provided the final assembly utilizing advanced TSV packaging technologies such as copper pillar bumping and mass reflow bonding. This is a pivotal demonstration of the heterogeneous die integration approach. A silicon process node or package interconnect density can either preserve or limit inter-chip communication when comparing SoC versus SiP approaches. Connecting two dual-core Cortex-A9 processors within a single package illustrated the expansion of function through multiple die. The test vehicle also implies that a large IC can be re-architected into smaller constituents to increase yield or design flexibility. By utilizing the best technology node for price and performance, 2.5D packaging can lower overall system cost of ownership or conversely, can expand overall performance through multiple high performance ICs. Chip designers are facing increased complexity and higher costs in order to move to smaller IC geometries and the adoption of 2.5D TSV technology will increase the options of construction (one vs. multiple die/SoCs). Having the flexibility to design with one or multiple die while maintaining high performance levels can offset the real estate costs of advanced nodes, permit silicon die reuse, improve yield and decrease overall product risk. The designer must choose the most appropriate silicon and assembly processes that satisfy the needs of each of the major functions in the overall system. Amkor's assembly process for this key product construction has been demonstrated on a range of products for the communications, graphics and the mobile markets. Process flexibility has been a key factor in addressing different markets and package complexity.

scholarly journals VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

2012 ◽  
pp. 40-46
Author(s):  
Mr.M.V. Sathish ◽  
Mrs. Sailaja
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Vlsi Architecture ◽  
Clock Frequency ◽  
Parallel Multiplier ◽  
Hybrid Type ◽  
Standard Design ◽  
Overall Performance ◽  
And Performance

A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

scholarly journals Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
‘Aqilah binti Abdul Tahrim ◽  
Huei Chaeng Chin ◽  
Cheng Siong Lim ◽  
Michael Loong Peng Tan
Keyword(s):  
High Speed ◽  
Average Power ◽  
Full Adder ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Subthreshold Region ◽  
And Performance ◽  
Power Delay Product ◽  
20 Nm

The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate (TG), and Hybrid CMOS (HCMOS). The performance of 1-bit FinFET-based full adder in 16-nm technology is benchmarked against conventional MOSFET-based full adder. The Predictive Technology Model (PTM) and Berkeley Shortchannel IGFET Model-Common Multi-Gate (BSIM-CMG) 16 nm low power libraries are used. Propagation delay, average power dissipation, power-delay-product (PDP), and energy-delay-product (EDP) are analysed based on all four types of full adder cell designs of both FETs. The 1-bit FinFET-based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and EDP is evident in the 1-bit FinFET-based full adder of CPL, giving the best overall performance due to its high-speed performance and good current driving capabilities.

Development of High Performance Moisture Separator Reheater

2009 ◽  
Author(s):  
Issaku Fujita ◽  
Kotaro Machii ◽  
Teruaki Sakata
Keyword(s):  
High Speed ◽  
Nuclear Power ◽  
High Performance ◽  
Power Plants ◽  
Tube Bundle ◽  
Separation Performance ◽  
Heating Steam ◽  
Severe Erosion ◽  
Moisture Separator ◽  
And Performance

Moisture Separator Reheaters (MSRs) of Nuclear power plants, especially 1st generation type (commercial operation started from between 1970 and 1982), has been suffered from various problems like severe erosion, moisture separation performance deterioration, drain sub cooling. To solve these problems and performance improvement, improved MSR was developed. At the new MSR, high performance SS439 stainless steel round type tube bundle was applied, where heating steam distribution is optimized by orifice plate in order to minimize the drain sub cooling. Based on the CFD approach, cycle steam distribution was optimized and FAC resistant material application for the internal parts of MSRs was determined. As a result, pressure drop was reduced by 0.6% against the HP turbine exhaust pressure. Performance of moisture separation was improved by the latest chevron type separator. Where, the reverse pressure is locally caused at the drainage area of the separator because remarkable longitudinal pressure distribution is formed by the high-speed steam flow in the manifold. Then, a new moisture separation structure was developed in consideration of the influence that this reverse pressure gave to the separator performance.

scholarly journals Design of 2.5D Interposer in High Bandwidth Memory and Through Silicon Via for High Speed Signal

2020 ◽  
Author(s):  
Bo Pu
Keyword(s):  
Artificial Intelligence ◽  
High Speed ◽  
High Performance ◽  
Equivalent Model ◽  
Electrical Characteristics ◽  
Through Silicon Via ◽  
High Bandwidth ◽  
Signal Path ◽  
High Speed Switching ◽  
Performance Computing

<p>The 2.5D interposer becomes a crucial solution to realize grand bandwidth of HBM for the increasing data requirement of high performance computing (HPC) and Artificial Intelligence (AI) applications. To overcome high speed switching bottleneck caused by the large resistive and capacitive characteristics of interposer, design methods to achieve an optimized performance in a limited routing area are proposed. Unlike the conventional single through silicon via (TSV), considering the reliability, multiple TSV are used as the robust 3D interconnects for each signal path. An equivalent model to accurately describe the electrical characteristics of the multiple TSVs, and a configuration pattern strategy of TSV to mitigate crosstalk are also proposed.</p>

Dual Die Package Design Strategy and Performance

2005 ◽  
Author(s):  
Mahadevan Suryakumar ◽  
Lu-Vong T. Phan ◽  
Mathew Ma ◽  
Wajahat Ahmed
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
High Performance ◽  
Clock Cycle ◽  
Average Power ◽  
Cost Effective ◽  
Design Strategy ◽  
Leakage Power ◽  
Memory Accesses ◽  
And Performance

The alarming growth of power increase has presented numerous packaging challenges for high performance processors. The average power consumed by a processor is the sum of dynamic and leakage power. The dynamic power is proportional to V^2, while the leakage current (therefore leakage power) is proportional to V^b where V is the voltage and b>1 for modern processes. This means lowering voltage reduces energy consumed per clock cycle but reduces the maximum frequency at which the processor can operate at. Since reducing voltage reduces power faster than it does frequency, integrating more cores into the processor would result in better performance/power efficiency but would generate more memory accesses, driving a need for larger cache and high speed signaling [1]. In addition, the design goal to create unified package pinout for both single core and multicore product flavors adds additional constraint to create a cost effective package solution for both market segments. This paper discusses the design strategy and performance of dual die package to optimize package performance for cost.

scholarly journals Impact of Modern Virtualization Methods on Timing Precision and Performance of High-Speed Applications

2019 ◽  
Vol 11 (8) ◽  
pp. 179 ◽  
Author(s):  
Veronika Kirova ◽  
Kirill Karpov ◽  
Eduard Siemens ◽  
Irina Zander ◽  
Oksana Vasylenko ◽  
...  
Keyword(s):  
Virtual Environments ◽  
Virtual Environment ◽  
High Speed ◽  
High Performance ◽  
Estimation Accuracy ◽  
Network Applications ◽  
High Speed Network ◽  
Timing Precision ◽  
And Performance ◽  
The Impact

The presented work is a result of extended research and analysis on timing methods precision, their efficiency in different virtual environments and the impact of timing precision on the performance of high-speed networks applications. We investigated how timer hardware is shared among heavily CPU- and I/O-bound tasks on a virtualized OS as well as on bare OS. By replacing the invoked timing methods within a well-known application for estimation of available path bandwidth, we provide the analysis of their impact on estimation accuracy. We show that timer overhead and precision are crucial for high-performance network applications, and low-precision timing methods usage, e.g., the delays and overheads issued by virtualization result in the degradation of the virtual environment. Furthermore, in this paper, we provide confirmation that, by using the methods we intentionally developed for both precise timing operations and AvB estimation, it is possible to overcome the inefficiency of standard time-related operations and overhead that comes with the virtualization. The impacts of negative virtualization factors were investigated in five different environments to define the most optimal virtual environment for high-speed network applications.

Suspension Design for High-Performance Two-Axle Freight Vehicles

1969 ◽  
Vol 184 (4) ◽  
pp. 22-36 ◽  
Author(s):  
A. H. Wickens ◽  
A. O. Gilchrist ◽  
A. E. W. Hobbs
Keyword(s):  
High Speed ◽  
High Performance ◽  
Performance Criteria ◽  
Test Vehicle ◽  
Suspension Parameters ◽  
Suspension Performance ◽  
Freight Vehicles

The paper outlines the principal suspension performance criteria which need to be satisfied when two-axle vehicles are operated at high speed. The derivation of a set of suspension parameters to meet these criteria is discussed. Suspension designs which realize these parameters are described. A test vehicle fitted with this design of suspension has been built and the results of track tests are given.

scholarly journals Wavelength-division-multiplexing (WDM)-based integrated electronic–photonic switching network (EPSN) for high-speed data processing and transportation

Nanophotonics ◽  
2020 ◽  
Vol 9 (15) ◽  
pp. 4579-4588
Author(s):  
Chenghao Feng ◽  
Zhoufeng Ying ◽  
Zheng Zhao ◽  
Jiaqi Gu ◽  
David Z. Pan ◽  
...  
Keyword(s):  
Wavelength Division Multiplexing ◽  
High Speed ◽  
High Performance ◽  
Performance Enhancement ◽  
Switching Network ◽  
Photonic Switching ◽  
Wavelength Division ◽  
High Speed Data ◽  
And Performance ◽  
Performance Computing

AbstractIntegrated photonics offers attractive solutions for realizing combinational logic for high-performance computing. The integrated photonic chips can be further optimized using multiplexing techniques such as wavelength-division multiplexing (WDM). In this paper, we propose a WDM-based electronic–photonic switching network (EPSN) to realize the functions of the binary decoder and the multiplexer, which are fundamental elements in microprocessors for data transportation and processing. We experimentally demonstrate its practicality by implementing a 3–8 (three inputs, eight outputs) switching network operating at 20 Gb/s. Detailed performance analysis and performance enhancement techniques are also given in this paper.

scholarly journals Study on the Follow-up Measurement of Goodwill of Listed Companies

2020 ◽  
Vol 4 (2) ◽  
pp. 55
Author(s):  
Zhuang Yan ◽  
Xiang Youcai
Keyword(s):  
Capital Market ◽  
High Performance ◽  
Information Quality ◽  
Listed Companies ◽  
International Standards ◽  
Distribution Analysis ◽  
Performance Impact ◽  
Key Factor ◽  
And Performance

Nowadays, the wave of mergers and acquisitions in the capital market is still surging. High evaluation does bring high performance, and the huge impairment of goodwill has become a key factor for the frequent Black Swan events of listed companies. Starting from the essence of goodwill, using Chinese A-share listed companies from 2007 to 2019 as samples and based on the market data, distribution analysis and performance impact, this paper argues that problems of goodwill impairment in China are incomplete accounting standards, inexhaustive impairment implementation and incomprehensive market supervision, thus giving reasonable suggestions. Proper follow-up measurement of goodwill is conducive to improving accounting information quality and adapting to capital market demands, which is of great significance to the revision of international standards.

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