Low Residual Stress and High Performance Dielectric for WLP (Wafer Level Packaging) Applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001559-001584
Author(s):  
Raymond Thibault ◽  
Michael Gallagher ◽  
Kevin Wang ◽  
Matthew Yonkey ◽  
Duane Romer ◽  
...  
Keyword(s):  
Mechanical Properties ◽  
Residual Stress ◽  
Vertical Integration ◽  
Chemical Stability ◽  
High Performance ◽  
Dielectric Materials ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Advanced Packaging ◽  
3D Chip Stacking

The advanced packaging application space continues to evolve as mobile devices pack more and more features into a limited space. This feature concentration is causing a deviation from the conventional shrinkage pathway predicted by Moore's law which, in turn, requires dielectric materials with ever more rigid thermal, chemical, and mechanical properties to meet the challenging requirements of next generation packages such as TSV and 3D chip stacking. One such challenge is the thinner substrates required for vertical integration in TSV and 3D packages. Cured dielectrics impart stress onto the underlying substrate and this wafer bow will only magnify with thinner substrates. Designing photodielectrics with inherently lower residual stress will greatly aide in the development of materials to meet future advanced packaging needs. This presentation will outline the development of a new photodielectric material that builds upon the excellent thermal, electrical, and chemical stability of BCB-based materials while providing a significant reduction in residual stress.

Residual Stress in Silicon Caused by Cu-Sn Wafer-Level Packaging

2013 ◽  
Author(s):  
Maaike M. V. Taklo ◽  
Astrid-Sofie Vardøy ◽  
Ingrid De Wolf ◽  
Veerle Simons ◽  
H. J. van de Wiel ◽  
...  
Keyword(s):  
Residual Stress ◽  
Integrated Circuit ◽  
High Performance ◽  
White Light Interferometry ◽  
Wafer Level ◽  
Noticeable Effect ◽  
Micro Raman Spectroscopy ◽  
Wafer Level Packaging ◽  
Mems Device ◽  
Specific Technology

The level of stress in silicon as a result of applying Cu-Sn SLID wafer level bonding to hermetically encapsulate a high-performance infrared bolometer device was studied. Transistors are present in the read out integrated circuit (ROIC) of the device and some are located below the bond frame. Test vehicles were assembled using Cu-Sn SLID bonding and micro-Raman spectroscopy was applied on cross sectioned samples to measure stress in the silicon near the bond frame. The test vehicles contained cavities and the bulging of the structures was studied using white light interferometry. The test vehicles were thermally stressed to study possible effects of the treatments on the level of stress in the silicon. Finite element modeling was performed to support the understanding of the various observations. The measurements indicated levels of stress in the silicon that can affect transistors in regions up to 15 μm below the bond frame. The observed levels of stress corresponded well with the performed modeling. However, no noticeable effect was found for the ROIC used in this work. The specific technology used for the fabrication of the ROIC of a MEMS device is thus decisive. The level of stress did not appear to change as a result of the imposed thermal stress. The level of stress caused by the bond frame can be expected to stay constant throughout the lifetime of a device.

Functionalization and Tip-open of Carbon Nanotubes for High-Performance Symmetric Supercapacitor

2021 ◽  
Author(s):  
Yaxiong Zhang ◽  
Erqing Xie
Keyword(s):  
Mechanical Properties ◽  
Carbon Nanotubes ◽  
Aspect Ratio ◽  
Specific Surface ◽  
Surface Area ◽  
Chemical Stability ◽  
High Aspect Ratio ◽  
High Performance ◽  
Large Specific Surface Area ◽  
Symmetric Supercapacitor

Carbon nanotubes (CNTs) have been widely studied as supercapacitor electrodes because of their excellent conductivity, high aspect ratio, excellent mechanical properties, chemical stability, and large specific surface area. However, the...

Robust Reliability Performance of Large size eWLB (Fan-out WLP)

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001438-001457 ◽  
Author(s):  
Seung Wook Yoon
Keyword(s):  
Form Factor ◽  
Dielectric Materials ◽  
Structural Defects ◽  
Temperature Cycle ◽  
Wafer Level ◽  
Component Level ◽  
Wafer Level Packaging ◽  
Large Size ◽  
Reliability Performance ◽  
Robust Reliability

With reducing form-factor and functional integration of mobile devices, Wafer Level Packaging (WLP) is attractive packaging technology with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP, it is more optimal and promising solution compared to fan-in WLP, because it can offer greater flexibility in design of more IOs, multi-chips, heterogeneous integration and 3D SiP. eWLB (embedded wafer level packaging) is a type of fan-out WLP enabling applications that require smaller form-factor, excellent heat dissipations, thin package profile as it has the potential to evolve in various configurations with proven manufacturing capacity and production yield. This paper discusses the recent advancements of robust reliability performance of large size eWLB. It will also highlight the recent achievement of enhanced component level reliability with advanced dielectric materials. After a parametric study and mechanical simulations, new advanced materials were selected and applied to eWLB. Standard JEDEC tests were carried out to investigate component level reliability of large size (9x9~14x14mm2) test vehicles and both destructive/non-destructive analysis were performed to investigate potential structural defects. Daisychain test vehicles were also tested for drop and TCoB (Temperature Cycle on Board) reliability performance in industry standard test conditions. Besides, this paper will also present a study of package level warpage behaviour with Thermo-Moire measurement.

Low Temperature Curing - Aqueous Base Developable Photoimageable Dielectric for WLP (Wafer Level Packaging)

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000986-001015
Author(s):  
Eric Huenger ◽  
Joe Lachowski ◽  
Greg Prokopowicz ◽  
Ray Thibault ◽  
Michael Gallagher ◽  
...  
Keyword(s):  
Low Temperature ◽  
Dielectric Material ◽  
Broad Band ◽  
Dielectric Materials ◽  
Next Generation ◽  
Wafer Level ◽  
Moore’S Law ◽  
Moore's Law ◽  
3D Chip Stacking ◽  
The Impact

As advanced packaging application space evolves and continues to deviate from the conventional shrinkage pathway predicted by Moore's law, material suppliers need to continue to work with OEMs, OSATs and Foundries to identify specific opportunities. One such opportunity continues to present itself in developing new materials to support new platforms for next generation products to support 3D chip stacking and TSV applications. The newer material sets can be established to meet more challenging design requirements associated with the demands, presented by the application from both a physical/lithographical processing and design perspective. Next generation packages requires the development of new dielectric materials that can support both the physical demands of 3D chip stacking and TSV package design aspects while maintaining strengths of the existing material platform. While vertical integration necessitates the use of thinned substrates and its associated integration challenges, there is a continuing need to support horizontal shrinkage typical of the Moore's Law, which pushes the lithography envelope requiring finer pitch and smaller feature resolution capability. This presentation identifies the strategy we have taken and highlights approach taking in the development of low temperature curable photoimageable dielectric materials with enhanced lithographic performance. We will discuss the methodology used to create benzocyclobutene based dielectric material curable at 180 °C and show how lithographic performance can be tuned to allow sub 5 micron via using broad band illumination. Finally we will review the impact of low temperature processing on the mechanical, thermal and electrical properties of this novel photoimageable dielectric material.

Improved compensation for a reduction stepper to meet the challenges for advanced packaging applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000814-000819 ◽  
Author(s):  
James E Webb ◽  
Steven Gardner ◽  
Elvino DaSilveira
Keyword(s):  
Leading Edge ◽  
Image Features ◽  
Wafer Level ◽  
Projection Lens ◽  
Wafer Level Packaging ◽  
Alignment System ◽  
Wide Range ◽  
Advanced Packaging ◽  
Volume Production ◽  
Mix And Match

Advanced packaging manufacturers require steppers that will provide solutions for the challenges encountered with new advances in wafer-level packaging technologies such as TSV, eWLB, silicon and glass interposers being utilized in leading edge mobile devices. Step and repeat photolithography systems capable of finer imaging with tighter overlay are being introduced to meet the challenging manufacturing requirements associated with the mix and match needed for volume production on larger wafers. A 2X reduction stepper with unique features incorporated that extend the range of compensation is necessary to achieve the tighter specifications needed for many advanced packaging applications printed on 300 to 450mm wafers. A high throughput projection optical system is used to expose circuit patterns from a reticle mask onto a substrate to image features with the optimal fidelity required for advanced packaging technologies. The camera incorporates 350–450nm light from a mercury arc lamp that is transmitted through the mask containing circuit patterns. The imaging field prints a large 52mm × 66mm area in a single exposure. These features enable a system to process wafers in fewer shots which result in higher throughput using lower power. Substrates are positioned with a precise X, Y, Θ stage by locating marks using an off-axis, bright field alignment system with fully trainable mark feature capability. The approach results in precisely placed features within a layer and from layer to layer without directly referencing the reticle. The integrated metrology and precision positioning subsystem technologies are combined with a low distortion projection lens and a wide range of adjustments, allowing the stepper to be integrated into a production line in a mix and match setup with other lithography systems. This equipment can be used to image critical layers on substrates while ensuring grid registration and alignment with other lithography systems that are also printing images in the same process line. Several important global and intra-field image placement relationships for devices requiring multiple layer patterning have been combined in the stepper matching correction software. Further adjustment to the tool can be made to improve overlay when incorporated with fab-wide yield management software for automated, real-time process control. The types of adjustments needed and techniques that can be applied to compensate for image placement errors over large areas are discussed.

A 3‐dB Quadrature WLP Coupler for 60 GHz Applications

2012 ◽  
Vol 1427 ◽  
Author(s):  
Hamid Kiumarsi ◽  
Hiroyuki Ito ◽  
Noboru Ishihara ◽  
Kenichi Okada ◽  
Yusuke Uemichi ◽  
...  
Keyword(s):  
Insertion Loss ◽  
High Performance ◽  
Low Cost ◽  
Phase Error ◽  
Superior Performance ◽  
60 Ghz ◽  
Wafer Level ◽  
Chip Area ◽  
Wafer Level Packaging ◽  
Coupled Lines

ABSTRACTA 60 GHz tandem coupler using offset broadside coupled lines is proposed in a WLP (Wafer Level Packaging) technology. The fabricated coupler has a core chip area of 750 μm × 385 μm (0.288 mm2). The measured results show an insertion loss of 0.44 dB, an amplitude imbalance of 0.03 dB and a phase difference of 87.6° at 60 GHz. Also the measurement shows an insertion loss of less than 0.67 dB, an amplitude imbalance of less than 0.31 dB, a phase error of less than 3.7°, an isolation of more than 29.7 dB and a return loss of more than 27.9 dB at the input ant coupled ports and more than 14.3 dB at the direct and isolated ports over the frequency band of 57-66 GHz, covering 60 GHz band both in Japan and US. To the best of our knowledge the proposed coupler achieves the lowest ever reported insertion loss and amplitude imbalance for a 3-dB coupler on a silicon substrate. With its superior performance and lower cost compared to the CMOS counterparts, the proposed coupler is a suitable candidate for low-cost high-performance millimeter-wave systems.

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