Residual Stress in Silicon Caused by Cu-Sn Wafer-Level Packaging

2013 ◽  
Author(s):  
Maaike M. V. Taklo ◽  
Astrid-Sofie Vardøy ◽  
Ingrid De Wolf ◽  
Veerle Simons ◽  
H. J. van de Wiel ◽  
...  
Keyword(s):  
Residual Stress ◽  
Integrated Circuit ◽  
High Performance ◽  
White Light Interferometry ◽  
Wafer Level ◽  
Noticeable Effect ◽  
Micro Raman Spectroscopy ◽  
Wafer Level Packaging ◽  
Mems Device ◽  
Specific Technology

The level of stress in silicon as a result of applying Cu-Sn SLID wafer level bonding to hermetically encapsulate a high-performance infrared bolometer device was studied. Transistors are present in the read out integrated circuit (ROIC) of the device and some are located below the bond frame. Test vehicles were assembled using Cu-Sn SLID bonding and micro-Raman spectroscopy was applied on cross sectioned samples to measure stress in the silicon near the bond frame. The test vehicles contained cavities and the bulging of the structures was studied using white light interferometry. The test vehicles were thermally stressed to study possible effects of the treatments on the level of stress in the silicon. Finite element modeling was performed to support the understanding of the various observations. The measurements indicated levels of stress in the silicon that can affect transistors in regions up to 15 μm below the bond frame. The observed levels of stress corresponded well with the performed modeling. However, no noticeable effect was found for the ROIC used in this work. The specific technology used for the fabrication of the ROIC of a MEMS device is thus decisive. The level of stress did not appear to change as a result of the imposed thermal stress. The level of stress caused by the bond frame can be expected to stay constant throughout the lifetime of a device.

Low Residual Stress and High Performance Dielectric for WLP (Wafer Level Packaging) Applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001559-001584
Author(s):  
Raymond Thibault ◽  
Michael Gallagher ◽  
Kevin Wang ◽  
Matthew Yonkey ◽  
Duane Romer ◽  
...  
Keyword(s):  
Mechanical Properties ◽  
Residual Stress ◽  
Vertical Integration ◽  
Chemical Stability ◽  
High Performance ◽  
Dielectric Materials ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Advanced Packaging ◽  
3D Chip Stacking

The advanced packaging application space continues to evolve as mobile devices pack more and more features into a limited space. This feature concentration is causing a deviation from the conventional shrinkage pathway predicted by Moore's law which, in turn, requires dielectric materials with ever more rigid thermal, chemical, and mechanical properties to meet the challenging requirements of next generation packages such as TSV and 3D chip stacking. One such challenge is the thinner substrates required for vertical integration in TSV and 3D packages. Cured dielectrics impart stress onto the underlying substrate and this wafer bow will only magnify with thinner substrates. Designing photodielectrics with inherently lower residual stress will greatly aide in the development of materials to meet future advanced packaging needs. This presentation will outline the development of a new photodielectric material that builds upon the excellent thermal, electrical, and chemical stability of BCB-based materials while providing a significant reduction in residual stress.

A 3‐dB Quadrature WLP Coupler for 60 GHz Applications

2012 ◽  
Vol 1427 ◽  
Author(s):  
Hamid Kiumarsi ◽  
Hiroyuki Ito ◽  
Noboru Ishihara ◽  
Kenichi Okada ◽  
Yusuke Uemichi ◽  
...  
Keyword(s):  
Insertion Loss ◽  
High Performance ◽  
Low Cost ◽  
Phase Error ◽  
Superior Performance ◽  
60 Ghz ◽  
Wafer Level ◽  
Chip Area ◽  
Wafer Level Packaging ◽  
Coupled Lines

ABSTRACTA 60 GHz tandem coupler using offset broadside coupled lines is proposed in a WLP (Wafer Level Packaging) technology. The fabricated coupler has a core chip area of 750 μm × 385 μm (0.288 mm2). The measured results show an insertion loss of 0.44 dB, an amplitude imbalance of 0.03 dB and a phase difference of 87.6° at 60 GHz. Also the measurement shows an insertion loss of less than 0.67 dB, an amplitude imbalance of less than 0.31 dB, a phase error of less than 3.7°, an isolation of more than 29.7 dB and a return loss of more than 27.9 dB at the input ant coupled ports and more than 14.3 dB at the direct and isolated ports over the frequency band of 57-66 GHz, covering 60 GHz band both in Japan and US. To the best of our knowledge the proposed coupler achieves the lowest ever reported insertion loss and amplitude imbalance for a 3-dB coupler on a silicon substrate. With its superior performance and lower cost compared to the CMOS counterparts, the proposed coupler is a suitable candidate for low-cost high-performance millimeter-wave systems.

SiP(System in Package) Solutions with Wafer Level Packaging Technology

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002226-002253 ◽  
Author(s):  
In Soo Kang ◽  
Jong Heon (Jay) Kim
Keyword(s):  
Embedded System ◽  
High Performance ◽  
Low Cost ◽  
Wafer Level ◽  
Molding Compound ◽  
Wafer Level Packaging ◽  
Ic Packaging ◽  
Chip Size ◽  
Bonding Technology ◽  
Small Form Factor

In mobile application, the WLP technology has been developing to make whole package size almost same as chip size. However, the I/O per chip unit area has increased so that it gets difficult to realize ideal pad pitch for better reliability. Recently, to achieve the thin and small size, high performance and low cost semiconductor package, Embedding Die and Fanout Technologies have been suggested and developed based on wafer level processing. In this work, as a solution of system in package, wafer level embedded package and fanout technology will be reviewed. Firstly, Wafer level embedded System in Package (WL-eSiP) which has daughter chip (small chip) embedded inside mother chip (bigger chip) without any special substrate has been suggested and developed. To realize wafer level embedded system in package (WL-eSiP), wafer level based new processes like wafer level molding for underfilling and encapsulation by molding compound without any special substrate have been applied and developed, including high aspect ratio Cu bumping, mold thinning and chip-to-wafer flipchip bonding. Secondly, Fan-out Package is considered as alternative package structure which means merged package structure of WLCSP (wafer level chip size package) and PCB process. We can make IC packaging widen area for SIP(System in Package) or 3D package. In addition, TSV and IPD are key enabling technology to meet market demands because TSV interconnection can provide wider bandwidth and high transmission speed due to vertical one compared to wire bonding technology and IPD can provide higher performance, more area saving to be assembled and small form factor compared to discrete passive components.

Wafer Level Package for MEMS with TSVs and Hermetic Seal

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002314-002335
Author(s):  
Akinori Shiraishi ◽  
Mitsutoshi Higashi ◽  
Kei Murayama ◽  
Yuichi Taguchi ◽  
Kenichi Mori
Keyword(s):  
Silicon Wafer ◽  
Adhesive Bonding ◽  
Anodic Bonding ◽  
Back Side ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Mems Device ◽  
Bonding Method ◽  
Wafer Level Package

In recent years, downsizing of MEMS package and high accuracy MEMS device mounting have been strongly required from expanding applications that using MEMS not only for industrial and automobile but also for consumer typified mobile phone. In order to achieve that, it is appropriate to use Silicon package that can be mounted at wafer level packaging. Silicon package is made of monocrystal silicon wafer. The deep cavity is fabricated on monocrystal silicon wafer by Wet or Dry etching. And MEMS device can be mounted on the cavity. The electrical connecting between front side and back side of cavity portion is achieved by TSVs that located on the bottom of cavity. Hermetic seal can be achieved by using glass or silicon wafer bonding method. By using a driver device wafer (before dicing) as the cap for hermetic seal, smaller size and smaller number of parts module can be fabricated. In this report, methods and designs for hermetic seal with wafer level process were examined. Methods that applied were polyimide adhesive bonding, anodic bonding and Au-In solder bonding. Location of TSVs on the bottom of cavity and thickness of diaphragm with TSVs was also examined. Silicon package for piezo type gyro MEMS that designed by the result of evaluation was fabricated. This package used optimized Au-In solder bonding for hermetic seal and optimized location of TSVs for interconnection. That was designed over 50% thinner than conventional ceramic packages. Characteristics of hermetic seal were evaluated by Q factor of gyro MEMS that mounted inside of the silicon package. It is confirmed that performance of sealing are good enough for running of the MEMS.

Fine Pitch(40μm) Integration Platform for Flexible Hybrid Electronics using Fan-Out Wafer-level Packaging

2018 ◽  
Vol 2018 (1) ◽  
pp. 000064-000068
Author(s):  
Amir Hanna ◽  
Arsalan Alam ◽  
G. Ezhilarasu ◽  
Subramanian S. Iyer
Keyword(s):  
High Performance ◽  
Metal Films ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Integration Platform ◽  
Wafer Level Packaging ◽  
Fine Pitch ◽  
Mechanical Bending

Abstract A flexible fan-out wafer-level packaging (FOWLP) process for heterogeneous integration of high performance dies in a flexible and biocompatible elastomeric package (FlexTrateTM) was used to assemble 625 dies with co-planarity and tilt <1μm, average die-shift of 3.28 μm with σ < 2.23 μm. Fine pitch interconnects (40μm pitch) were defined using a novel corrugated topography to mitigate the buckling phenomenon of metal films deposited on elastomeric substrates. Corrugated interconnects were then used to interconnect 200 dies, and then tested for cyclic mechanical bending reliability and have shown less than 7% change in resistance after bending down to 1 mm radius for 1,000 cycles.

Temporary Bonding and Debonding Technologies to Enable Innovative Fan-Out Embedded Interposer for High-Density Applications

2015 ◽  
Vol 2015 (1) ◽  
pp. 1-6
Author(s):  
Alvin Lee ◽  
Jay Su ◽  
Xiao Liu ◽  
Yin-Po Hung ◽  
Yu-Min Lin ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Process Integration ◽  
Dielectric Material ◽  
Wafer Level ◽  
Additive Process ◽  
Bonding Material ◽  
Wafer Level Packaging ◽  
Ic Packaging ◽  
Temporary Bonding

As requirements increase for mobile devices to be lighter and thinner and to operate at high speed and high bandwidth, innovations in wafer-level packaging have evolved to 3-D structures, such as package-on-package (PoP), fan-out integration, and through-silicon-via (TSV) interposer architectures. However, wafer-level packaging is still considered to be costly and slow in throughput due to wafer size limitations. In this study, temporary bonding and debonding processes using mechanical or laser release technologies were applied in the fabrication process of an integrated embedded glass interposer as a foundation for 3-D integrated circuit (IC) packaging on panel-level packaging. Glass interposers having dimensions of 10 mm × 10 mm and a thickness of 120 μm were fabricated. The interposers had through-glass vias (TGVs) 25 μm in diameter and 3000 I/O pads of copper under-bump metallization (UBM) and were designed as a nearly full-array type. The interposers were supported by a temporary bonding material on silicon or glass wafers and embedded by built-up dielectric material on which fan-out redistribution circuit layers were deposited. For forming the pattern of the redistribution layer, a UV laser was used to form 75-μm-diameter blind vias, and conductive interconnections were made by a semi-additive process (SAP) using photolithography and electrolytic copper. The process of building up layers from the glass interposer to form an embedded fan-out interposer can eliminate a joining process required by traditional 2.5-D IC integration. Finally, the embedded fan-out carrier is separated from the glass or silicon wafer through a laser debonding process. An experiment to study the correlation of bonding material and release material with built-up lamination in backside processes will be discussed in this paper to address full process integration on panel-size substrates. The combination of temporary bonding technology with mechanical or laser release technologies will pave the way for realizing cost-effective 3-D IC packaging on panel-level substrates.

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