Spheron Fan-In WLCSP Technology Qualification and Scale Up - 200 mm to 300 mm

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000471-000494
Author(s):  
Andre Cardoso ◽  
Rui Almeida ◽  
Felandorio Fernandes ◽  
Ted Tessier ◽  
Anthony Curtis
Keyword(s):  
Crucial Role ◽  
High Performance ◽  
Scale Up ◽  
High Density ◽  
Technology Licensing ◽  
Ic Packaging ◽  
Wafer Processing ◽  
Unit Reduction

Overview: Fan-In WLP plays crucial role on today's high density, high performance IC Packaging. 300 mm wafer processing addresses cost-per-unit reduction and volume demand. Results of Spheron Fan-In WLCSP Technology Qualification and 200 mm to 300 mm Scale Up at Nanium, using FlipChipInternational Technology Licensing

Recent Advances in Thin Film Multilayer Interconnect Technology for IC Packaging

1987 ◽  
Vol 108 ◽  
Author(s):  
Ronald J. Jensen
Keyword(s):  
Thin Film ◽  
Recent Work ◽  
High Performance ◽  
High Density ◽  
High Conductivity ◽  
Packaging Technology ◽  
Ic Packaging ◽  
The Stability ◽  
Work Done ◽  
Interconnect Technology

ABSTRACTA high-performance packaging technology being developed at Honeywell and a number of other companies uses thin-film processes to pattern high-density interconnections in multiple layers of a high-conductivity conductor (e.g., copper) and a polymer dielectric, primarily polyimide. This paper describes the physical characteristics and unique advantages of this thin film multilayer (TFML) interconnect technology; it then summarizes the results of recent work done at Honeywell in processing TFML structures, assessing the stability and reliability of the materials system, and fabricating test vehicles and demonstration packages.

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

Impact of Metal Pad Etch-Induced Plasma Damage on Dynamic Retention Time Degradation during High Temperature Stress in High Density DRAM Technology

2005 ◽  
Author(s):  
D-J Kim ◽  
I-G Kim ◽  
J-Y Noh ◽  
H-J Lee ◽  
S-H Park ◽  
...  
Keyword(s):  
High Temperature ◽  
Temperature Stress ◽  
Retention Time ◽  
High Temperature Stress ◽  
High Density ◽  
Cell Junction ◽  
Antenna Effect ◽  
Plasma Damage ◽  
Root Cause ◽  
Wafer Processing

Abstract As DRAM technology extends into 12-inch diameter wafer processing, plasma-induced wafer charging is a serious problem in DRAM volume manufacture. There are currently no comprehensive reports on the potential impact of plasma damage on high density DRAM reliability. In this paper, the possible effects of floating potential at the source/drain junction of cell transistor during high-field charge injection are reported, and regarded as high-priority issues to further understand charging damage during the metal pad etching. The degradation of block edge dynamic retention time during high temperature stress, not consistent with typical reliability degradation model, is analyzed. Additionally, in order to meet the satisfactory reliability level in volume manufacture of high density DRAM technology, the paper provides the guidelines with respect to plasma damage. Unlike conventional model as gate antenna effect, the cell junction damage by the exposure of dummy BL pad to plasma, was revealed as root cause.

scholarly journals A Brief Overview of On-Chip Voltage Regulation in High-Performance and High-Density Integrated Circuits

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 813-826
Author(s):  
Farid Uddin Ahmed ◽  
Zarin Tasnim Sandhie ◽  
Liaquat Ali ◽  
Masud H. Chowdhury
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Voltage Regulation ◽  
High Density ◽  
On Chip

Highly doped and exposed Cu(i)–N active sites within graphene towards efficient oxygen reduction for zinc–air batteries

2016 ◽  
Vol 9 (12) ◽  
pp. 3736-3745 ◽  
Author(s):  
Haihua Wu ◽  
Haobo Li ◽  
Xinfei Zhao ◽  
Qingfei Liu ◽  
Jing Wang ◽  
...  
Keyword(s):  
Oxygen Reduction ◽  
Active Sites ◽  
High Performance ◽  
High Density ◽  
Catalyst Loading ◽  
Zinc Air Batteries

High-density coordination unsaturated copper(i)–nitrogen embedded in graphene demonstrates a high performance and stability in primary zinc–air batteries with ultralow catalyst loading.

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