Development of Lead Free Plating Chemical for Various Applications

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000944-000967
Author(s):  
Takeshi Hatta ◽  
Atsushi Ishikawa ◽  
Takuma Katase ◽  
Akihiro Masuda
Keyword(s):  
Chemical Stability ◽  
High Speed ◽  
Flip Chip ◽  
New Technologies ◽  
High Reliability ◽  
Lead Free ◽  
Current Status ◽  
Chip Technology ◽  
Solder Bumps ◽  
Pure Sn

Flip chip connection has been applied to a lot of applications to shorten the connection length for high performance. Solder bumping is one of the key technologies for flip chip connection, and its quality strongly brings large impact on the reliability after packaging. Electroplating is one of the methods to form solder bumps. And Sn-Ag is considered as the first candidate of lead free alloy for electroplating method. We have released Sn-Ag plating chemical and it has been used by many customers in the world. In the future, flip chip technology will progress to further miniaturization and high integration with the new technologies such as Cu pillar and Through Silicon Via (TSV). At that time, further variations of alloys are necessary for electroplating method to meet various requirements. Even for Sn-Ag plating chemical, higher plating rate is required to improve productivity in mass production. In this time, we have developed new Sn-Ag high speed plating chemical based on our conventional technology. Furthermore, we have succeeded to develop Pure Sn and Sn-Cu chemicals for bumping method to meet customer's requirement. Sn-Cu is considered as a good candidate for bumping alloy to achieve high reliability, but the chemical stability is not so good. Therefore, we successfully modified the Sn-Cu chemical and extended chemical stability. We will update our current status about high speed Sn-Ag plating chemical and other chemicals like Sn-Cu and pure Sn in this time. By using these binary alloy chemicals, we are able to produce Sn-Ag-Cu solder bumps by stacking Sn-Ag and Sn-Cu. And it can bring further variation for bumping alloys.

Advanced Microelectronics Packaging Solutions for Miniaturized Medical Devices

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001963-001976
Author(s):  
Rabindra Das ◽  
Steven Rosser ◽  
Frank Egitto
Keyword(s):  
Flip Chip ◽  
New Technologies ◽  
High Reliability ◽  
Present Report ◽  
Flexible Substrate ◽  
System Level ◽  
Organic Substrates ◽  
Internal Layers ◽  
Microelectronics Packaging ◽  
Wide Range

The wide range of applications for medical electronics drives unique requirements that can differ significantly from commercial & military electronics. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. In the present report, key enablers for achieving reduction in size, weight, and power (SWaP) in electronic packaging for a variety of medical applications are discussed. Advanced microelectronics packaging solutions with embedded passives are enabling SWaP reductions. Implementation of these solutions has realized up to 27X reduction in physical size for existing PWB assemblies, with significant reductions in weight. Shorter interconnects can also reduce or eliminate the need for termination resistors for some net topologies. Successful miniaturized products integrate the following design techniques and technologies: component footprint reduction, thin high density interconnects substrate technologies, I/O miniaturization and IC assembly capabilities. This paper presents fabrication and electrical characterization of embedded actives and passives on organic multilayered substrates. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on embedded chips, resistors, and capacitors. Embedded passive technology further enhances miniaturization by enabling components to be moved from the surface of the substrate to its internal layers. The use of thin film resistor material allows creating individual miniaturized buried resistors. These resistors provide additional length and width reduction with negligible increases to the overall substrate and module (SiP) height. Resistor values can vary from 5 ohm to 50 Kohm with tolerances from 5 to 20% and areas as small as 0.2 mm2. The embedded resistors can be laser trimmed to a tolerance of <5% for applications that require tighter tolerance. The electrical properties of embedded capacitors fabricated from polymer-ceramic nanocomposites showed a stable capacitance and low loss over a wide frequency and temperature range. A few test vehicles were assembled to do system level analysis. Manufacturing methods and materials for producing advanced organic substrates and flex along with ultra fine pitch assemblies are discussed. A case study detailing the fabrication of a flexible substrate for use in an intravascular ultrasound (IVUS) catheter demonstrates how the challenges of miniaturization are met. These challenges include use of ultra-thin polymer films, extreme fine-feature circuitization, and assembly processes to accommodate die having reduced die pad pitch. In addition, new technologies for embedding a variety of active chips are being developed. A variety of active chips, including a chip having dimensions of one millimeter square, have been embedded and electrically connected to develop high performance packages.

Control of Bump Morphology in Lead Free Solder Plating for Higher Density Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001643-001669
Author(s):  
Koji Tatsumi ◽  
Kyouhei Mineo ◽  
Takeshi Hatta ◽  
Takuma Katase ◽  
Masayuki Ishikawa ◽  
...  
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
New Technologies ◽  
Short Circuit ◽  
Lead Free Solder ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Different Shapes ◽  
Free Solder ◽  
High Density Packaging

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation. We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary. This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed. With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming. In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes. We'd like to present our updates on controlling bump morphology for various applications.

Molding Recipe Study for MUF Solder Crack Improvement

2018 ◽  
Vol 2018 (1) ◽  
pp. 000121-000124
Author(s):  
Scott Chen ◽  
Leander Liang ◽  
Pallas Hsu ◽  
Tim Tsai ◽  
Mason Liang ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Flow Simulation ◽  
Test Vehicle ◽  
Chip Technology ◽  
Solder Bumps ◽  
Capillary Underfill ◽  
Mold Flow ◽  
Profile Reduction ◽  
Transfer Pressure

Abstract In recent years, flip chip technology becomes more and more important with benefits of thin package profile, reduction of package outline, and excellent electrical and thermal performance by connection of copper pillar bumps (CuP) or C4 solder bumps. In order to fill the die gap to prevent voids problem, two encapsulated solutions could be applied: capillary underfill (CUF) and molded underfill (MUF). In general comparison, CUF means to dispense underfill first to fill in die gap then proceed over-molding afterward; and MUF is directly fill under and above die by mold compound. The advantages of MUF solution are low cost and high throughput, however, it will suffer other assembly issues such as solder extrusion and solder crack, and might result in potential function failure. To form these kinds of defects, we suspected that solder will plastically deform under thermal stress treatment, which comes from unbalance mold transfer pressure and material expansion stress during thermal process. In this article, we have tried to investigate the mechanism of solder crack through molding recipe DOE (Design of Experiment) and mold flow simulation. The test vehicle is 12 × 12 mm2 FCCSP, with 6 × 5 mm2 die size. The bump type is copper pillar bump and pitch/size are 126 um and 35 × 60 um2, respectively. The molding recipe has been evaluated by cross section, and it revealed that molding transfer time and molding temperature are directions toward improvement of solder crack issue.

High Productivity Thermo-Compression Flip Chip Bonding

2014 ◽  
Vol 2014 (1) ◽  
pp. 000100-000106
Author(s):  
Tom Colosimo ◽  
Horst Clauberg ◽  
Evan Galipeau ◽  
Matthew B. Wasserman ◽  
Michael Schmidt-Lange ◽  
...  
Keyword(s):  
High Speed ◽  
Large Scale ◽  
Flip Chip ◽  
Solder Joints ◽  
Rapid Heating ◽  
Temperature Cycle ◽  
Temperature Uniformity ◽  
Heating Rates ◽  
Heating And Cooling ◽  
Chip Technology

Advancements in electronic packaging performance and cost have historically been driven by higher integration primarily provided by fab shrinks that has followed the well-known Moore's law. However, due to the tremendous and continuously increasing cost of building new fabs, the performance/cost improvements achieved via node shrinks are negated. This leaves packaging innovation as the vehicle to achieve future cost-performance improvements. This has initiated a More-than-Moore idea that has led to vigorous R&D in packaging. Advanced packages which employ ultra-fine pitch flip chip technology for chip-to-substrate, chip-to-chip, or chip-to-interposer for the first level interconnect have been developed as an answer to obtaining higher performance. However, the costs are too high as compared to traditional wire bonding. The status today is that the fundamental technical hurdles of manufacturing the new advanced packages have been solved, but cost reduction and yield improvements have to be addressed for large-scale adoption into high volume manufacturing. In traditional flip chip assembly silicon chips are tacked onto a substrate and then the solder joints are melted and mass reflowed in an oven. This mass reflow technique is troublesome as the pitch of the solder bumps become finer. This is due to the large differences in the thermal expansion coefficient of the die and the substrate, which creates stress at the solder joints and warpage of the package when the die and substrate are heated and cooled together. To mitigate and resolve this issue, thermo-compression bonders have been developed which locally reflow the solder without subjecting the entire substrate to the heating and cooling cycle. This requires that the bondhead undergo heating past the melting point of solder and then cooling down to a low enough temperature to pick the next die from the wafer that is mounted to tape. Machines in the market today can accomplish this temperature cycle in 7 to 15 seconds. This is substantially slower than the standard flip chip process which leads to high cost and is delaying the introduction of these new packages. This paper shows a flip chip bonder with a new heating and cooling concept that will radically improve the productivity of thermo-compression bonding. Data and productivity cycles from this new bond head with heating rates of over 200°C/sec and cooling of faster than 100°C/sec are revealed. Experimental results are shown of exceptional temperature accuracy across the die of 5°C throughout the cycle and better than 3°C at the final heating stage. The high speed thermo-compression bonds are analyzed and the efficacy of the new concept is proven. Excellent temperature uniformity while heating rapidly is an absolute necessity for enabling good solder joints in a fast process. Without good temperature uniformity, additional dwell times need to be incorporated to allow heat to flow to all of the joints, negating any benefits from rapid heating. Whereas the current state-of-that-art is often to program temperature in steps, this bonder can be commanded and accurately follows more complex temperature profiles with great accuracy. Examples of how this profiling can be used to enhance the uniformity and integrity of the joints with non-conductive pastes, film, and without underfill along with the associated productivity improvements will be shown. Tests that show portability across platforms that will lead to set up time and yield improvements and are identified and quantified. Additionally new ideas for materials and equipment development to further enhance productivity and yield are explored.

Study on electromigration in flip chip lead-free solder connections with 40 μm or 30 μm diameter on thin film ceramic substrates

2015 ◽  
Vol 2015 (1) ◽  
pp. 000799-000805
Author(s):  
Marek Gorywoda ◽  
Rainer Dohle ◽  
Bernd Kandler ◽  
Bernd Burger
Keyword(s):  
Thin Film ◽  
High Stability ◽  
Flip Chip ◽  
Lead Free ◽  
Published Data ◽  
Organic Substrates ◽  
Lead Free Solder ◽  
Ceramic Substrates ◽  
Solder Bumps ◽  
Free Solder

Electromigration comprises one of the processes affecting the long-term reliability of electronic devices; it has therefore been the focus of many investigations in recent years. In regards to flip chip packaging technology, the majority of published data is concerned with electromigration in solder connections to metallized organic substrates. Hardly any information is available in the literature on electromigration in lead-free solder connections on thin film ceramic substrates. This work presents results of a study of electromigration in lead-free (SAC305) flip chip solder bumps with a nominal diameter of 40 μm or 30 μm with a pitch of 100 μm on silicon chips assembled onto thin film Al2O3 ceramic substrates. The under bump metallization (UBM) comprised of a 5 μm thick electroless nickel immersion gold (ENIG) layer directly deposited on the AlCu0.5 trace. The ceramic substrates were metallized using a thin film multilayer (NiCr-Au(1.5 μm)-Ni(2 μm) structure on the top of which wettable areas were produced with high precision by depositing flash Au (60 nm) of the required diameter (40 μm or 30 μm). All electromigration tests were performed at the temperature of 125 °C. Initially, one chip assembly with 40 μm and one with 30 μm solder bumps was loaded with the current density of 8 kA/cm2 for 1,000 h. The assemblies did not fail and an investigation with SEM revealed no significant changes to the microstructure of the bumps. Thereafter seven chip assemblies with 40 μm solder bumps and five assemblies with 30 μm bumps were subjected to electromigration tests of 14 kA/cm2 or 25 kA/cm2, respectively. Six of the 40 μm-assemblies failed after 7,000 h and none of the 30 μm-assemblies failed after 2,500 h of test duration so far. Investigation of failed samples performed with SEM and EDX showed asymmetric changes of microstructure in respect to current flow. Several intermetallic phases were found to form in the solder. The predominant damage of the interconnects was found to occur at the cathode contact to chip; the Ni-P layers there showed typical columnar Kirkendall voids caused by migration of Ni from the layers into the solder. Failure of the contacts apparently occurred at the interface between Ni-P and solder. In summary, the results of the study indicate a very high stability of lead-free solder connections on ceramic substrates against electromigration. This high stability is primarily due to a better heat dissipation and thus to a relatively low temperature increase of the ceramic packages caused by resistive heating during flow of electric current. In addition, the type of the metallization used in the study seems to be more resistant to electromigration than the standard PCB metallization as it does not contain a copper layer.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Evaluation of a Conductive Adhesive Based Approach to Lead Free Flip Chip Assembly

2002 ◽  
Author(s):  
Muthiah Venkateswaran ◽  
Peter Borgesen ◽  
K. Srihari
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Critical Evaluation ◽  
Conductive Adhesive ◽  
Circuit Board ◽  
Lead Free ◽  
Conductive Adhesives ◽  
Flip Chip Assembly ◽  
Placement Machine

Electrically conductive adhesives are emerging as a lead free, flux less, low temperature alternative to soldering in a variety of electronics and optoelectronics applications. Some of the potential benefits are obvious, but so far the adhesives have some limitations as well. The present work offers a critical evaluation of one approach to flip chip assembly, which lends itself particularly well to use with a high speed placement machine. Wafers were bumped by stencil printing of a thermoset conductive adhesive, which was then fully cured. In assembly, the conductive adhesive paste was stencil printed onto the pads of a printed circuit board and cured after die placement. The printing process was optimized to ensure robust assembly and the resulting reliability assessed.

A Model for Underfill Viscous Flow Considering the Resistance Induced by Solder Bumps

2004 ◽  
Vol 126 (2) ◽  
pp. 186-194 ◽  
Author(s):  
Chyi-Lang Lai ◽  
Wen-Bin Young
Keyword(s):  
Flip Chip ◽  
External Pressure ◽  
Good Prediction ◽  
Parallel Plates ◽  
Rectangular Array ◽  
Chip Technology ◽  
Solder Bumps ◽  
Proposed Model ◽  
Filling Time ◽  
Underfill Flow

During the underfill process, polymers driven by either capillary force or external pressure are filled at a low speed between the chip and substrate. Current methods treated the flow in the chip cavity as a laminar flow between parallel plates, which ignored the resistance induced by the solder bumps or other obstructions. In this study, the filling flow between solder bumps was simulated by a flow through a porous media. By using the superposition of flows through parallel plates and series of rectangular ducts, permeability of the underfill flow was fully characterized by the geometric arrangement of solder bumps and flat chips. The flow resistances caused by adjacent bumps were represented in its permeability. The model proposed in this study could provide a numerical approach to approximate and simulate the undefill process for flip-chip technology. Although the proposed model is applicable for any geometric arrangement of solder bumps, rectangular-array of solder bumps layout was used first for comparison with experimental results of other article. Comparisons of the flow-front shapes and filling time with the experimental data indicated that the flow simulation obtained from the proposed model gave a good prediction for the underfill flow.

Robust Design Analysis on Fatigue Life of Lead-Free Sn0.5Ag Solder in a Multichip Module Package

2013 ◽  
Vol 284-287 ◽  
pp. 375-379 ◽  
Author(s):  
Chieh Kung
Keyword(s):  
Fatigue Life ◽  
Integrated Circuits ◽  
Robust Design ◽  
High Speed ◽  
Flip Chip ◽  
Design Analysis ◽  
Influential Factor ◽  
Fatigue Reliability ◽  
Chip Technology ◽  
Ic Package

System-in-package (SiP) has become a mainstream technology in IC package industry as it provides the solutions to the growing needs of high speed functions, mobility/portability, energy efficiency, and miniaturization of electronic products. One special form of SiP is the multi-chip module (MCM) in which multiple integrated circuits (ICs), semiconductor dies or other discrete components are packaged onto a unifying substrate. Thus, the reliability of package integrity becomes one of the major reliability concerns. In the present paper, a robust design analysis on the thermo-mechanical reliability of an MCM package with flip-chip technology is demonstrated. Our results show that for the specific package, the CTE of the substrate is the most influential factor to the fatigue reliability of the package. The optimal combination of the parameters is recommended. The robust design analysis optimizes the fatigue life from 165 cycles to 1080 cycles which is a 554.5% gain on the fatigue life.

Experimental Study of Void Formation in Eutectic and Lead-Free Solder Bumps of Flip-Chip Assemblies

2005 ◽  
Vol 128 (3) ◽  
pp. 202-207 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Experimental Study ◽  
Heat Flux ◽  
Flip Chip ◽  
Void Formation ◽  
Lead Free ◽  
Void Volume ◽  
Lead Free Solder ◽  
Solder Bumps ◽  
Free Solder ◽  
High Lead

This paper reports the experimental findings of void formation in eutectic and lead-free solder joints of flip-chip assemblies. A previous theory indicated that the formation of voids is determined by the direction of heating. The experiments were designed to examine the size and location of voids in the solder samples subject to different heat flux directions. A lead-free solder (Sn-3.5Ag-0.75Cu) and a eutectic solder (63Sn37Pb) were employed in the experiments. Previous experiments [Wang, D., and Panton, R. L., 2005, “Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies,” ASME J. Electron. Packag., 127(2), pp. 120–126; 2005, “Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps,” ASME J. Electron. Packag., 127(4), pp. 440–445] employed a high lead solder. 288 solder bumps were processed for each solder. Both eutectic and lead-free solder have shown fewer voids and much smaller void volume than those for high-lead solder. Compared with lead-free solder, eutectic solder has a slightly lower void volume and a lower percentage of defective bumps. For both eutectic and lead-free solders, irrespective of the cooling direction, heating solder samples from the top shows fewer defective bumps and smaller void volume. No significant effect on void formation for either eutectic or lead-free solder was found via reversing the heat flux direction during cooling. Unlike high-lead solder, small voids in eutectic or lead-free solder comprised 35-88% of the total void volume. The final distribution of voids shows a moderate agreement with thermocapillary theory, indicating the significance of the temperature gradient on the formation of voids.

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