A Model for Underfill Viscous Flow Considering the Resistance Induced by Solder Bumps

2004 ◽  
Vol 126 (2) ◽  
pp. 186-194 ◽  
Author(s):  
Chyi-Lang Lai ◽  
Wen-Bin Young
Keyword(s):  
Flip Chip ◽  
External Pressure ◽  
Good Prediction ◽  
Parallel Plates ◽  
Rectangular Array ◽  
Chip Technology ◽  
Solder Bumps ◽  
Proposed Model ◽  
Filling Time ◽  
Underfill Flow

During the underfill process, polymers driven by either capillary force or external pressure are filled at a low speed between the chip and substrate. Current methods treated the flow in the chip cavity as a laminar flow between parallel plates, which ignored the resistance induced by the solder bumps or other obstructions. In this study, the filling flow between solder bumps was simulated by a flow through a porous media. By using the superposition of flows through parallel plates and series of rectangular ducts, permeability of the underfill flow was fully characterized by the geometric arrangement of solder bumps and flat chips. The flow resistances caused by adjacent bumps were represented in its permeability. The model proposed in this study could provide a numerical approach to approximate and simulate the undefill process for flip-chip technology. Although the proposed model is applicable for any geometric arrangement of solder bumps, rectangular-array of solder bumps layout was used first for comparison with experimental results of other article. Comparisons of the flow-front shapes and filling time with the experimental data indicated that the flow simulation obtained from the proposed model gave a good prediction for the underfill flow.

Molding Recipe Study for MUF Solder Crack Improvement

2018 ◽  
Vol 2018 (1) ◽  
pp. 000121-000124
Author(s):  
Scott Chen ◽  
Leander Liang ◽  
Pallas Hsu ◽  
Tim Tsai ◽  
Mason Liang ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Flow Simulation ◽  
Test Vehicle ◽  
Chip Technology ◽  
Solder Bumps ◽  
Capillary Underfill ◽  
Mold Flow ◽  
Profile Reduction ◽  
Transfer Pressure

Abstract In recent years, flip chip technology becomes more and more important with benefits of thin package profile, reduction of package outline, and excellent electrical and thermal performance by connection of copper pillar bumps (CuP) or C4 solder bumps. In order to fill the die gap to prevent voids problem, two encapsulated solutions could be applied: capillary underfill (CUF) and molded underfill (MUF). In general comparison, CUF means to dispense underfill first to fill in die gap then proceed over-molding afterward; and MUF is directly fill under and above die by mold compound. The advantages of MUF solution are low cost and high throughput, however, it will suffer other assembly issues such as solder extrusion and solder crack, and might result in potential function failure. To form these kinds of defects, we suspected that solder will plastically deform under thermal stress treatment, which comes from unbalance mold transfer pressure and material expansion stress during thermal process. In this article, we have tried to investigate the mechanism of solder crack through molding recipe DOE (Design of Experiment) and mold flow simulation. The test vehicle is 12 × 12 mm2 FCCSP, with 6 × 5 mm2 die size. The bump type is copper pillar bump and pitch/size are 126 um and 35 × 60 um2, respectively. The molding recipe has been evaluated by cross section, and it revealed that molding transfer time and molding temperature are directions toward improvement of solder crack issue.

Spatial analysis of underfill flow in flip-chip encapsulation

2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Fei Chong Ng ◽  
Mohd Hafiz Zawawi ◽  
Mohamad Aizat Abas
Keyword(s):  
Spatial Analysis ◽  
Formation Mechanism ◽  
Flip Chip ◽  
Void Formation ◽  
Past Research ◽  
Air Entrapment ◽  
Time Model ◽  
Content Type ◽  
Filling Time ◽  
Underfill Flow

Purpose The purpose of the study is to investigate the spatial aspects of underfill flow during the flip-chip encapsulation process, for instance, meniscus evolution and contact line jump (CLJ). Furthermore, a spatial-based void formation mechanism during the underfill flow was formulated. Design/methodology/approach The meniscus evolution of underfill fluid subtended between the bump array and the CLJ phenomenon were visualized numerically using the micro-mesh unit cell approach. Additionally, the meniscus evolution and CLJ phenomenon were modelled analytically based on the formulation of capillary physics. Meanwhile, the mechanism of void formation was explained numerically and analytically. Findings Both the proposed analytical and current numerical findings achieved great consensus and were well-validated experimentally. The variation effects of bump pitch on the spatial aspects were analyzed and found that the meniscus arc radius and filling distance increase with the pitch, while the subtended angle of meniscus arc is invariant with the pitch size. For larger pitch, the jump occurs further away from the bump entrance and takes longer time to attain the equilibrium meniscus. This inferred that the concavity of meniscus arc was influenced by the bump pitch. On the voiding mechanism, air void was formed from the air entrapment because of the fluid-bump interaction. Smaller voids tend to merge into a bigger void through necking and, subsequently, propagate along the underfill flow. Practical implications The microscopic spatial analysis of underfill flow would explain fundamentally how the bump design will affect the macroscopic filling time. This not only provides alternative visualization tool to analyze flow pattern in the industry but also enables the development of accurate analytical filling time model. Moreover, the void formation mechanism gave substantial insights to understand the root causes of void defects and allow possible solutions to be formulated to tackle this issue. Additionally, the microfluidics sector could also benefit from these spatial analysis insights. Originality/value Spatial analysis on underfill flow is scarcely conducted, as the past research studies mainly emphasized on the temporal aspects. Additionally, this work presented a new mechanism on the void formation based on the fluid-bump interaction, in which the formation and propagation of micro-voids were numerically visualized for the first time. The findings from current work provided fundamental information on the flow interaction between underfill fluid and solder bump to the package designers for optimization work and process enhancement.

Regional Segregation With Spatial Considerations-Based Analytical Filling Time Model for Non-Newtonian Power-Law Underfill Fluid in Flip-Chip Encapsulation

2019 ◽  
Vol 141 (4) ◽  
Author(s):  
Fei Chong Ng ◽  
Aizat Abas ◽  
M. Z. Abdullah
Keyword(s):  
Power Law ◽  
Flip Chip ◽  
Current Model ◽  
Process Time ◽  
Time Model ◽  
Package Design ◽  
Absolute Value ◽  
Filling Time ◽  
Underfill Flow ◽  
Encapsulation Process

Abstract This paper presents a new analytical filling time model to predict the flow of non-Newtonian underfill fluid during flip-chip encapsulation process. The current model is formulated based on the regional segregation approach, instead of the conventional porous media approximation. In this approach, the filling times were computed separately at different filling stages, before being summed up till the required filling distance. The non-Newtonian property of underfill fluid is modeled using the conventional power-law constitutive equation. Additionally, the spatial aspects of the underfill flow were incorporated into the present analysis. For instance, the evolution of underfill menisci from convex to concave was analytically developed and the contact line jump (CLJ) criterion was improved using minimal flow assumption. Upon validated with three distinct past underfill experiments, the current analytical model is found to have the best performance as it predicted the filling times with the least discrepancy among other existing filling time models. Quantitatively, the discrepancies were averagely reduced by an absolute value of at least 8.68% and 4.90%, respectively, for the first two set of validation studies. Generally, this model is particularly useful in manufacturing lines to estimate the process time of flip-chip underfill, as well as for the optimizations of process and package design.

A Theoretical Analysis of the Concept of Critical Clearance Toward a Design Methodology for the Flip-Chip Package

2007 ◽  
Vol 129 (4) ◽  
pp. 473-478 ◽  
Author(s):  
J. W. Wan ◽  
W. J. Zhang ◽  
D. J. Bergstrom
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Flow Characteristics ◽  
Quantitative Relation ◽  
Package Design ◽  
Solder Bumps ◽  
Filling Time ◽  
Encapsulation Process ◽  
Advanced Packaging ◽  
Gap Height

In this article, we present a theoretical study on the concept known as critical clearance for flip-chip packages. The critical clearance phenomenon was first observed in an experiment reported by Gordon et al. (1999, “A Capillary-Driven Underfill Encapsulation Process,” Advanced Packaging, 8(4), pp. 34–37). When the clearance is below a critical value, filling time begins to increase dramatically, and when the clearance is above this value, the influence of clearance on filling time is insignificant. Therefore, the optimal solder bump density in a flip-chip package should be one with a clearance larger than the critical clearance. The contribution of our study is the development of a quantitative relation among package design features, flow characteristics, and critical clearance based on an analytical model we developed and reported elsewhere. This relation is further used to determine critical clearance given a type of underfill material (specifically the index n of the power-law constitutive equation), the solder bump pitch, and the gap height; further the flip-chip package design can be optimized to make the actual clearance between solder bumps greater than its corresponding critical clearance.

Prediction of Electromigration Critical Current Density in Passivated Arbitrary-Configuration Interconnect

2019 ◽  
Vol 141 (2) ◽  
Author(s):  
Yasuhiro Kimura ◽  
Masumi Saka
Keyword(s):  
Critical Current Density ◽  
Critical Current ◽  
Current Density ◽  
Flip Chip ◽  
Electrical Potential ◽  
Atomic Density ◽  
Configuration Model ◽  
Chip Technology ◽  
Arbitrary Configuration ◽  
Solder Bumps

A critical current density, a criterion of electromigration (EM) resistance in interconnects, above which EM damages initiate has been studied to minimize EM damages of interconnects. In general, the assessment of a critical current density is confined to straight interconnect called as Blech specimen, although the critical current density is sensitive to structural characteristic. This work proposes a procedure of predicting a critical current density for any arbitrary-configuration interconnect by using the analogy between atomic density and electrical potential. In the models of straight and barrel interconnects as the typical solder bumps in modern flip-chip technology, the critical current density is predicted through calculating electrical potential by proposed formulation and simulation based on the finite element analysis (FEA). The critical current density for straight interconnect obtained by experiment leads to numerically calculate the critical electrical potential, which is independent of interconnect configuration. The critical potential corresponds to the critical atomic density, below which the accumulation of atoms allows. The calculated critical electrical potential determines a critical current density for arbitrary-configuration interconnect including current crowding effect. This finding can predict a critical current density for actual arbitrary-configuration model and provide an insight for the applying to the packaging design such as ball grid array and C4 flip-chip solder bumps.

The effect of underfill on thermal stresses on logic ASIC and its electrical performance

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-20
Author(s):  
Babak Talebanpour ◽  
Doug Link
Keyword(s):  
Frequency Shift ◽  
Flip Chip ◽  
Thermal Stresses ◽  
Electrical Performance ◽  
Shear Stresses ◽  
Normal Stresses ◽  
Clock Frequency ◽  
Chip Technology ◽  
Solder Bumps ◽  
Solder Reflow

Flip chip technology is widely used today to support the demand for high interconnect density of modern microelectronic circuits. Conventionally, solder bumps have provided the electrical and mechanical connection between the chip and the substrate. The solder bumps are prone to fatigue and failure especially in large chips and/or mobile devices. Conventional underfilling process which consists of flowing an epoxy under the chip and curing it after the flip chip connections are made mechanically supports the assembly, significantly reducing the shear stresses on the bumps and minimizing the chip warpage due to thermal stresses. However, underfill also has side effects. The flow of underfill depends on a lot of parameters usually can be incomplete or containing a lot of voids, inconsistent underfill results in unpredictable overall durability or manufacturing survivability. Furthermore, underfilling introduces certain components of stress, this form of stress can have adverse effect on the electrical performance of the die if it occurs close to stress sensitive parts. In this study, the effect of underfilling and its quality on the clock frequency shift of a DSP (Digital Signal Processor) chip used by Starkey Hearing Technologies is investigated. Clock frequency measurements after a solder reflow process has been compared for different underfill materials, and underfill quality. Finite element analysis was implemented to assess the stress transferred to the clock circuit on the die and examine how existence of underfill, bump height, location of bumps, and underfill voids affect the stress. The following results have been concluded based on the work presented in this paper:The conventional underfilling process for dies with very small standoff heights can be very in consistent, strongly depending on the gap uniformity, flex traces, cleanliness of the package after solder reflow, etc. large percentage of delamination and voids can occur. The voids and delamination can cause solder extrusion as well as inconsistent stress distribution on the die.Although underfilling causes large normal stresses on the die, it reduces the effective stress on the die which can translate to less warpage and the problems associated with it.The height of the bumps does not strongly affect the amount of stress build up on the die if it does not compromise a uniform underfill.Relocation of the bumps away from the clock circuit significantly reduces the stress on the clock, and it has been shown to minimize the clock shift in practice. A minimum amount of distance between the clock circuit and solder bumps should be considered when DSP layout are designed.If the clock circuit surface is not in contact with the underfill, normal stresses will not be transferred to the clock circuit minimizing the clock frequency shift. The best approach to implement this method is wafer-level underfill technique. The underfill will be applied at the wafer fab and precision lasers can cut the underfill laminate at desired locations. This process can guarantee support for the die by a uniform underfill, while stress sensitive parts will be protected against unwanted thermal stresses.

Underfill Flow in Flip-Chip Encapsulation Process: A Review

2021 ◽  
Author(s):  
Fei Chong Ng ◽  
Mohamad Aizat Abas
Keyword(s):  
Flip Chip ◽  
Parametric Design ◽  
Microscopic Analysis ◽  
Technological Advancement ◽  
Filling Time ◽  
Underfill Flow ◽  
Encapsulation Process ◽  
Time Determination ◽  
Reliability Issue ◽  
Analytic Skills

Abstract The scope of review of this paper focused on the pre-curing underfilling flow stage of encapsulation process. A total of 80 related works has been reviewed and being classified into process type, method employed, and objective attained. Statistically showed that the conventional capillary is the most studied underfill process, while the numerical simulation was mainly adopted. Generally, the analyses on the flow dynamic and distribution of underfill fluids in the bump array aimed for the filling time determination as well as the predictions of void occurrence. Parametric design optimization was subsequently conducted to resolve the productivity issue of long filling time and reliability issue of void occurrence. The bump pitch was found to the most investigated parameter, consistent to the miniaturization demand. To enrich the design versatility and flow visualization aspects, experimental test vehicle was innovated using imitated chip and replacement fluid, or even being scaled-up. Nonetheless, the analytical filling time models became more accurate and sophiscasted over the years, despite still being scarce in number. With the technological advancement on analysis tools and further development of analytic skills, it was believed that the future researches on underfill flow will become more comprehensive, thereby leading to the production of better packages in terms of manufacturing feasibility, performances, and reliability. Lastly, few potential future works were recommended, for instance, microscopic analysis on the bump-fluid interaction, consideration of filler particles and incorporation of artificial intelligence.

Influence of Gap Height in Flip Chip Underfill Process With Non-Newtonian Flow Between Two Parallel Plates

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
C. Y. Khor ◽  
M. Z. Abdullah ◽  
M. Abdul Mujeebu
Keyword(s):  
Pressure Drop ◽  
Flip Chip ◽  
3D Model ◽  
Fluid Dynamic ◽  
Power Law Model ◽  
Parallel Plates ◽  
Newtonian Flow ◽  
Filling Time ◽  
Gap Height ◽  
Volume Method

In this paper, the finite volume method (FVM) is used for the simulation of flip chip underfill process by considering non-Newtonian flow between two parallel plates that emulate the silicon die and the substrate. 3D model of two parallel plates of size 12.75 mm × 9.5 mm with gap heights of 5 μm, 15 μm, 25 μm, 35 μm, 45 μm, and 85 μm are developed and simulated by computational fluid dynamic (CFD) code, fluent 6.3.26. The flow is modeled by using power law model and volume of fluid (VOF) technique is applied for flow front tracking. The effect of change in height of the gap between the plates on the underfill process is mainly studied in the present work. It is observed that the gap height has significant influence on the melt filling time and pressure drop, as the gap height decreases filling time and pressure drop increase. The simulation results are compared with previous experimental results and found in good conformity.

Development of Lead Free Plating Chemical for Various Applications

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000944-000967
Author(s):  
Takeshi Hatta ◽  
Atsushi Ishikawa ◽  
Takuma Katase ◽  
Akihiro Masuda
Keyword(s):  
Chemical Stability ◽  
High Speed ◽  
Flip Chip ◽  
New Technologies ◽  
High Reliability ◽  
Lead Free ◽  
Current Status ◽  
Chip Technology ◽  
Solder Bumps ◽  
Pure Sn

Flip chip connection has been applied to a lot of applications to shorten the connection length for high performance. Solder bumping is one of the key technologies for flip chip connection, and its quality strongly brings large impact on the reliability after packaging. Electroplating is one of the methods to form solder bumps. And Sn-Ag is considered as the first candidate of lead free alloy for electroplating method. We have released Sn-Ag plating chemical and it has been used by many customers in the world. In the future, flip chip technology will progress to further miniaturization and high integration with the new technologies such as Cu pillar and Through Silicon Via (TSV). At that time, further variations of alloys are necessary for electroplating method to meet various requirements. Even for Sn-Ag plating chemical, higher plating rate is required to improve productivity in mass production. In this time, we have developed new Sn-Ag high speed plating chemical based on our conventional technology. Furthermore, we have succeeded to develop Pure Sn and Sn-Cu chemicals for bumping method to meet customer's requirement. Sn-Cu is considered as a good candidate for bumping alloy to achieve high reliability, but the chemical stability is not so good. Therefore, we successfully modified the Sn-Cu chemical and extended chemical stability. We will update our current status about high speed Sn-Ag plating chemical and other chemicals like Sn-Cu and pure Sn in this time. By using these binary alloy chemicals, we are able to produce Sn-Ag-Cu solder bumps by stacking Sn-Ag and Sn-Cu. And it can bring further variation for bumping alloys.

A Surface Energy Approach to Developing an Analytical Model for the Underfill Flow Process in Flip-Chip Packaging

2021 ◽  
Author(s):  
X.J. Yao ◽  
Weijie Jiang ◽  
Jiahui Yang ◽  
Junjie Fang ◽  
W.J. (Chris) Zhang
Keyword(s):  
Surface Energy ◽  
Analytical Model ◽  
Flip Chip ◽  
Cfd Simulation ◽  
Flow Front ◽  
New Approach ◽  
Solder Bumps ◽  
Regular Triangle ◽  
Filling Time ◽  
Flip Chip Packaging

Abstract This paper presents a new approach to formulating an analytical model for the underfill process in flip-chip packaging to predict the flow front and the filling time. The new approach is based on the concept of surface energy along with the energy conservation principle. This approach avoids the need of modeling the flow path to predict the flow front and the filling time and thus it is suitable to different configurations of solder bumps, including different shapes and arrangements of solder bumps in flip-chip packaging. An experiment along with the CFD simulation was performed based on a proprietarily developed testbed to verify the effectiveness of this approach. Both the experimental and simulation results show that the proposed approach along with its model is accurate for flip-chip packages with different configurations besides the configuration of a regular triangle arrangement of solder bumps and a spherical shape of the solder bump.

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