Solutions for Wafer-Level Packaging of High Brightness LEDs

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001418-001442
Author(s):  
Thomas Uhrmann ◽  
B. Kim ◽  
T. Matthias ◽  
P. Lindner
Keyword(s):  
Form Factor ◽  
Light Output ◽  
High Volume ◽  
Performance Ratio ◽  
High Yield ◽  
Light Sources ◽  
Wafer Level ◽  
Process Step ◽  
High Brightness ◽  
The Cost

High brightness LEDs (HB-LEDs) carry a high prospect for general lighting applications. Competing with the cost/performance ratio of current light sources demands an increase of the overall efficiency as well as the reduction of the device cost. Since packaging accounts for 30%–50% of the cost of HB LED manufacturing, moving from die- level to wafer-level processes is one likely potential solution for reducing cost per lumen. Silicon-based WLP, using the established processing technology of the MEMS and IC industry, offers high fabrication reliability, high yield and the direct integration of the driver IC in the package. The already small form factor of WLP can be further reduced using Through-Silicon-Vias (TSV), increasing the maximum amount of chips per wafer. Silicon WLP also offers superior thermal management, with the relatively high thermal conductance of silicon. Redistributing LED dies on silicon wafer submounts, with metal bonding and copper TSVs, further improves the heat conductance away from the active region of the chip, resulting in increased device performance. Wafer-level optics can further improve performance and reduce packaging costs. Wafer-level lens molding based on imprint lithography is in high volume manufacture for cell phone camera modules. It allows creation of spherical and a-spherical lenses as well as lens stacks with minimized form factor. In contrast to the currently applied drop dispensing technique for LED lens fabrication, the shape of the lens can be accurately tailored and the decrease of the lens size results in lower absorption and higher light output. Most of these technologies are already in high volume production in other sectors. We will discuss the field proven solutions at each process step, from the formation of the silicon interposer, through the chip-to-wafer bonding, to the final imprinting of the wafer-level optics.

High-brightness LEDs of big chip size on multi-layer interconnects with optimized thermal dissipation and optical performance

2014 ◽  
Vol 2014 (1) ◽  
pp. 000877-000881
Author(s):  
Liang Wang ◽  
Gabe Guevara ◽  
Grant Villavicencio ◽  
Roseann Alatorre ◽  
Hala Shaba ◽  
...  
Keyword(s):  
Flip Chip ◽  
Wavelength Conversion ◽  
Light Output ◽  
Light Extraction ◽  
Thermal Dissipation ◽  
High Yield ◽  
Wafer Level ◽  
High Brightness ◽  
Aperture Ratio ◽  
Chip Size

The market share of high-brightness LEDs in general lighting has been rapidly expanding mainly owing to the continued technological advances on internal quantum efficiency, light extraction and wavelength conversion. In spite of these promising advances, there remain some key breakthroughs to be made before LED lighting technology can be fully adopted into the broad market, with emphasis on efficient thermal dissipation, higher efficacy at high brightness, and low manufacturing cost. Higher brightness requires LEDs to be operated at higher current density which results in efficacy degradation due to droop behavior and thus higher power loss into heat and shorter lifetime. Therefore a highly efficient mechanism of thermal dissipation is needed for timely conduction of heat away from the high-power LED chip. For general lighting at high brightness, a large chip size is preferable. More importantly, with larger chip size, higher brightness can be achieved at much lower current density which leads to less degradation of efficacy. However simply increasing the die size of LEDs in wafer fabrication causes significant yield loss and thus hinders the adoption of big-chip LEDs. In this paper we propose a scalable approach to enable larger chip sizes for manufacturing high efficacy & high brightness LEDs at high yield and low cost. The metric of lower cost per lumen is necessary for LEDs to be competitive to traditional light sources like fluorescent lights in the consumer market segment. About 50% of the total LED production cost is consumed by the packaging processes after the emissive device stack being fabricated. Also given the minimal thickness of the device stack, the key bottleneck for thermal dissipation resides in the packaging structure and its interface to the device stack. We address these two key challenges with a novel wafer-level packaging structure of metal contacts forming a perimeter that is integrated into the device stack, which optimizes the thermal dissipation rate from the active device stack to substrate while allowing high aperture ratio and improved light output. Our approach applies a wafer-level batch process starting from LED fabrication to packaging for internal and external light extraction as well as wavelength conversion, in order to achieve high throughput and high yield in a scalable and inexpensive manner. To improve the overall power efficiency, different materials have been selected for ohmic contacts and high reflectivity at p and n electrodes, and further developments continue to be implemented, including a current-spreading layer, large-area light extraction structure and integrated phosphor material. Flip chip packaging is chosen due to its advantage of full front-side emission, maximized aperture ratio, compact form factor, higher integration density and ease of wafer level processing. The substrates for flip chip packaging of LED chips are made of Si which was selected due to its relatively high thermal conductivity (149 W/m/K) and ease of fabrication with standard semiconductor processes. Multi-layer interconnects are patterned over the Si substrate with solder bumps built over the passivation openings for flip-chip assembly of multiple LED dies. The multi-layer dielectric stack of the substrate is designed to form dielectric mirror maximizing the reflection of emitted light back into the LED side for improved light output.

scholarly journals Roughing Milling with Ceramic Tools in Comparison with Sintered Carbide on Nickel-Based Alloys

Coatings ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 734
Author(s):  
Pablo Fernández-Lucio ◽  
Octavio Pereira Neto ◽  
Gaizka Gómez-Escudero ◽  
Francisco Javier Amigo Fuertes ◽  
Asier Fernández Valdivielso ◽  
...  
Keyword(s):  
Cutting Speed ◽  
High Volume ◽  
Cemented Carbide ◽  
Performance Ratio ◽  
Cost Performance ◽  
Ceramic Tools ◽  
The Cost ◽  
Engine Components ◽  
Coated Carbide ◽  
Milling Tools

Productivity in the manufacture of aircrafts components, especially engine components, must increase along with more sustainable conditions. Regarding machining, a solution is proposed to increase the cutting speed, but engines are made with very difficult-to-cut alloys. In this work, a comparison between two cutting tool materials, namely (a) cemented carbide and (b) SiAlON ceramics, for milling rough operations in Inconel® 718 in aged condition was carried out. Furthermore, both the influence of coatings in cemented carbide milling tools and the cutting speed in the ceramic tools were analysed. All tools were tested until the end of their useful life. The cost performance ratio was used to compare the productivity of the tested tools. Despite the results showing higher durability of the coated carbide tool, the ceramic tools presented a better behavior in terms of productivity at higher speed. Therefore, ceramic tools should be used for higher productivity demands, while coated carbide tools for low speed-high volume material removal.

300mm Wafer-Level Image Sensor Packaging

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000699-000716
Author(s):  
Thorsten Matthias ◽  
Bioh Kim ◽  
Gerald Mittendorfer ◽  
Paul Lindner ◽  
Moshe Kriman ◽  
...  
Keyword(s):  
Cost Reduction ◽  
High Volume ◽  
Image Sensor ◽  
Consumer Electronics ◽  
Glass Wafer ◽  
Wafer Level ◽  
Process Technology ◽  
Market Growth ◽  
The Cost ◽  
New Applications

The image sensor market is still showing s tremendous market growth due to applications in consumer electronics, medical, automotive and communication. For a lot of new applications the image sensor packaging is in fact the enabling key technology. The introduction of wafer level packaging a couple of years ago allowed the cost reduction necessary for high volume consumer electronics. Innovative packaging concepts with TSVs and thin dies enable unmatched form factor. Currently scaling image sensor manufacturing and packaging to 300mm is the next big step forward in cost reduction. Wafer level image sensor packaging requires capping of the sensor wafer with a glass wafer. This heterogeneous integration of silicon and glass results in a variety of challenges like thermal expansion mismatch and bow and warp of the wafer stack. In this paper Tessera's OptiML Micro Via Pad technology for image sensors will be described with a special emphasis on equipment and process technology. Wafer encapsulation, via formation, electrical routing, passivation and solder bumping will be discussed.

Packaging of High Brightness, Big-Chip LEDs

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001472-001492
Author(s):  
Lidia Lee ◽  
Paul Panaccione
Keyword(s):  
Form Factor ◽  
System Design ◽  
Light Output ◽  
Large Area ◽  
Plug And Play ◽  
High Brightness ◽  
Package Design ◽  
System Requirements ◽  
Lighting Systems ◽  
The Impact

A common approach for designing HB-LEDs into a variety of lighting systems is to arrange an array of many emitters over a large area in order to provide the required photometric flux. In certain applications, this common approach of arraying a large number of small chip LEDs introduces a number of challenges that can be solved by using a single package of big-chip LEDs with enough light output to meet the system requirements. This presentation will discuss package design for big-chip LEDs, compared to an array of many small emitter packages. In addition to big-chip package design, the impact on system design including optics, drivers, thermals, reliability, and form factor will be addressed. For illustration, a reference example will be presented in detail, consisting of an easy to use plug and play single package with 36mm2 of emitting area capable of up to 6000 lumens.

M-Series with Adaptive Patterning for High-Yield Fan-Out SIP

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000751-000773
Author(s):  
Craig Bishop ◽  
Suresh Jayaraman ◽  
Boyd Rogers ◽  
Chris Scanlan ◽  
Tim Olson
Keyword(s):  
New Technology ◽  
Minimum Size ◽  
High Yield ◽  
Wafer Level ◽  
Design Rules ◽  
Optical Scanner ◽  
Wafer Level Packaging ◽  
And Performance ◽  
The Cost ◽  
Semiconductor Chips

Fan-Out Wafer Level Packaging (FOWLP) holds immediate promise for packaging semiconductor chips with higher interconnect density than the incumbent Wafer Level Chip Scale Packaging (WLCSP). FOWLP enables size and performance capabilities similar to WLCSP, while extending capabilities to include multi-device system-in-packages. FOWLP can support applications that integrate multiple heterogeneously processed die at lower cost than 2.5D silicon interposer technologies. Current industry challenges with die position yield after die placement and molding result in low-density design rules and the high-cost of accurate die placement. Efficiently handling die shift is essential for making FOWLP cost-competitive with other technologies such as FCCSP and QFN. This presentation will provide an overview of Adaptive Patterning, a new technology for overcoming variability of die positions after placement and molding. In this process, an optical scanner is used to measure the true XY position and rotation of each die after panelization. The die measurements are then fed into a proprietary software engine that generates a unique pattern for each package. The resulting patterns are dispatched to a lithography system, which dynamically implements the unique patterns for all packages within a panel. For system-in-packages, this process offers a unique advantage over a fixed pattern: each die shift can be handled independently. With a fixed pattern, the design tolerances need to be large enough for all die to shift in opposing directions, otherwise yield loss in incurred. With Adaptive Patterning, vias and RDL features remain at minimum size and are matched to the measured die shift. The die-to-die interconnects are dynamically generated and account for the unique position of each die. Thus, Adaptive Patterning retains the same high-density design rules regardless of how many die are in a package. Adaptive Patterning provides the capability to use high-throughput die placement to drive down cost, while enabling higher-density system-in-package interconnect. With this technology the industry can finally realize the cost, flexibility, and form factor benefits of FOWLP.

Cost Analysis of TSV Process and Scaling Options

2014 ◽  
Vol 2014 (1) ◽  
pp. 000001-000007
Author(s):  
Victor Vartanian ◽  
Larry Smith ◽  
Klaus Hummler ◽  
Steve Olson ◽  
Brian Sapp ◽  
...  
Keyword(s):  
High Volume ◽  
Film Structure ◽  
Manufacturing Cost ◽  
Wafer Level ◽  
Factors Affecting ◽  
Multiple Process ◽  
Cost Of Materials ◽  
The Cost ◽  
The Impact ◽  
Cost Differences

SEMATECH evaluated the impact of various process options on the overall manufacturing cost of a TSV module, from TSV lithography and etch through post-plate CMP. The purpose of this work was to understand the cost differences of these options in order to identify opportunities to significantly reduce cost. Included in this study were multiple process and materials options for TSV etch, liner, and barrier/seed (B/S). For each of these options, recipes were adjusted for post-etch clean, ECD Cu fill and CMP overburden, and the resulting cost impacts were evaluated. The TSV dimensions used in this study are 5x50 μm and 2x40 μm. These cost comparisons included a sensitivity analysis, highlighting the main factors responsible for the differences. Cost of materials, tool cost, and throughput were the primary factors affecting cost differences, especially in barrier/seed deposition. In some cases the contributions from both these sources were comparable. We explain the assumptions used and some of the uncertainties inherent in this work. For example, where materials costs were significant, we extrapolated the cost of new materials from research quantities to those needed to support high volume manufacturing. We had to estimate throughputs and materials costs using our best engineering judgment, because the recipes have not yet been optimized. We also considered that the tools used on some non-critical steps might be fully depreciated, or a lower cost tool such as is used in wafer level packaging. Despite these uncertainties and assumptions, we were able to extract some fairly clear conclusions. The process options include the following B/S variations: For 5x50 μm TSVs, the B/S film structure is TaN/Ta/Ru/Cu, and the options are with and without the Ru and/or Cu layers. For 2x40 μm TSVs, the B/S structure is TaN/Ru/Cu, with different thicknesses of Ru, and the Cu is an optional seed layer for the field. We also discuss the impact of scaling the TSV dimensions on manufacturing costs. This work is continuing to look at different process options and to apply this methodology to MEOL modules such as temporary bond and debond, wafer thinning, and TSV reveal.

Fan-Out Packaging: Technologies and market trends

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-35 ◽  
Author(s):  
Jerome Azemar
Keyword(s):  
Cost Reduction ◽  
Business Models ◽  
Semiconductor Industry ◽  
Cost Benefit ◽  
High Volume ◽  
Main Trend ◽  
Wafer Level ◽  
Device Scaling ◽  
Application Processor ◽  
The Cost

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns to advanced packages. Emerging packages such as fan-out wafer level solution aim to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. In this work we will focus on Fan-Out packaging, an embedded package of most interest at the moment. The principle of Fan-Out technology is to embed products in a mold compound and allow redistribution layer pitch to be independent from die size. This approach is already mature for several years thanks to high volume products claimed by Nanium and JCET/Stats ChipPAC using eWLB type of Fan-Out, and with many other developments from OSATs and an aggressive technology from TSMC (inFO). 2016 was a turning point for the Fan-Out market with Apple A1O application processor being packaged using TSMC solution. This partnership changed the game and may create a trend of acceptance of Fan-Out packages for complex applications. The market for Fan-Out packages in 2016 already reached $500M, with potential breakthrough events in store in 2017 that could make the market reach $2B in 2020. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, capable of embedding complex ICs, other important OSATs like Powertech or Amkor are willing to enter the market with their own technologies. TSMC being the first example, foundries too could look at the OSATs reserved market through wafer-level packages, Samsung's reaction being interesting to follow. Each player has its own view on how to gain market share and meet the technical and financial challenges associated to Fan-Out packaging such as cost reduction, yield improvement, die shift… This work brings analysis of the strategies and offers of main players involved and describes potential success scenarios for them. It also helps to define what is Fan-Out Packaging and what are the different products and platforms, player per player, avoiding confusion already visible in the industry where many players call their solution a “Fan-Out” to benefit from the buzz created by Apple despite having significant differences from one to another (chip-first, chip-last, face-up, face-down, etc…). As package price represents the final verdict, carrier size evolution is also an important topic, both for wafers and panels, since it can help to drastically reduce the cost. This work shows that the main trend is still to keep wafer carriers but some players are already investing and developing panel-based solution and we expect volume production soon. While end-customers are pushing for a switch to panel, numerous challenges are limiting its widespread though. This work describes technical, economic and maturity challenges associated to panel manufacturing. Overall, the presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out packaging approaches by applications, business models and major players will be reviewed.

Chip Last Fan Out as an Alternative to Chip First

2015 ◽  
Vol 2015 (1) ◽  
pp. 000245-000250 ◽  
Author(s):  
Scott Chen ◽  
Simon Wang ◽  
Coltrane Lee ◽  
Adren Hsieh ◽  
John Hunt ◽  
...  
Keyword(s):  
Low Cost ◽  
Smart Phone ◽  
High Volume ◽  
Smart Phones ◽  
Portable Devices ◽  
Wafer Level ◽  
Packaging Technology ◽  
Two Factors ◽  
The Cost ◽  
Technology Nodes

Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, and they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), and system in package (SIP) being widely used in these smart phones & mobile devices.. Fan out WLCSP (FOWLP) has great potential to be the next new package for the smart phone mobility application. Two factors have driven fan out WLCSP (FOWLP) package technology in the last few years. The first is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solder ball interconnects. The second and potentially more important factor relates to the demand of the market for more functions. Not all silicon functionality benefits from these advanced nodes, and merely adds to the cost of the die. This has driven the designers to partitioning of desired functionality into multiple die, which in turn requires effective interconnection of these separate die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP). Up to date FOWLP used chip first processing, in which the bare die was molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers. We will describe a new alternative to chip first FOWLP, an alternative which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package has been in production in ASE for over a year, and uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm. Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented. We have designated this package structure “Fan Out Chip Last Package (FOCLP)” For higher end applications we will show the ability to use a high density substrate process for use in more demanding chip last fan out packages

Characterizations of Fan-out Wafer-Level Packaging

2017 ◽  
Vol 2017 (1) ◽  
pp. 000557-000562 ◽  
Author(s):  
Ming Li ◽  
Qingqian Li ◽  
John Lau ◽  
Nelson Fan ◽  
Eric Kuah ◽  
...  
Keyword(s):  
Good Control ◽  
High Yield ◽  
Glass Wafer ◽  
Wafer Level ◽  
Process Step ◽  
Wafer Level Packaging ◽  
Die Attach ◽  
Fabrication Defects ◽  
Electroplating Process ◽  
Test Chips

Abstract The calling for smaller form factor, higher I/O density, higher performance and lower cost has made fan-out wafer level packaging (FOWLP) technology the trend. Good control of die position accuracy and molded wafer warpage are some of the keys to achieve high-yield production for FOWLP. In this study, 10mm×10mm test chips were fabricated and attached (chip-first and die face-up) onto 12 inch glass wafer carriers using die-attach-film (DAF). These reconfigured wafers were compression-molded with selected epoxy molding compounds (EMC). Cu bumps (contact-pads) were revealed by grinding, and redistribution layers (RDLs) were fabricated by lithography and electroplating process. The fan-out wafers were evaluated and characterized after each process step with main focus on the die-misplacement/die shift, re-configured wafer warpage, compression molding defects and RDL fabrication defects. The root causes of these defects were investigated and analyzed, while the possible solutions to overcome the defects were proposed and discussed.

Transition From MEMS Technology to Nanofabrication

2007 ◽  
Author(s):  
T. Glinsner ◽  
P. Lindner ◽  
P. Kettner ◽  
H. Kirchberger
Keyword(s):  
Nanoimprint Lithography ◽  
Low Cost ◽  
High Volume ◽  
Laboratory Research ◽  
High Yield ◽  
Mems Devices ◽  
Wafer Level ◽  
Industrial Processing ◽  
The Past ◽  
Mems Technology

The successful commercialization of Micro-Electro-Mechanical Systems (MEMS) from R&D to off-the-shelf products and systems has evolved from laboratory research to reliable and low cost industrial processing methods over the past 20 years. Standardization, infrastructure, roadmaps and industrial associations have been deemed key contributors for a successful transition and adaptation of microelectronics fabrication techniques to a specific nature of manufacturing MEMS devices resulted in turn key solutions for low cost, high yield and high volume wafer level processing. The need for smaller feature sizes as well as low cost manufacturing solutions has lead to significant improvements of the classical optical lithography in the past two decades following Moore’s law. Alternative patterning techniques are under development worldwide for producing patterns in the nm-range. There are similarities between MEMS and Nanofabrication requirement that allow for transitioning standardized and reliable processing technology from wafer bonding to hot embossing and from wafer level packaging to μ-CP and UV-based Nanoimprint Lithography.

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