A High-Throughput Architecture for the SHA-256/224 Compliant With the DSRC Standard

2019 ◽  
Vol 10 (1) ◽  
pp. 98-118
Author(s):  
Imed Saad Ben Dhaou ◽  
Hannu Tenhunen
Keyword(s):  
High Throughput ◽  
Short Range ◽  
State Of The Art ◽  
High Level Synthesis ◽  
Data Flow Graph ◽  
Transformation Techniques ◽  
Safety Message ◽  
Dedicated Short Range Communication ◽  
Field Programmable ◽  
High Level

This article presents a word serial retimed architecture for the SHA-256/224 algorithm. The architecture is compliant with the dedicated-short range communication for safety message authentications. We elaborate three-operand adder architectures suitable for field programmable gate array implementation. Several transformation techniques at the data-flow-graph level have been used to derive the architecture. Synthesis results show that the architecture has high throughput/ slice value compared with state-of-the-art SHA-256 implementations. The article also promulgates a comparison between high-level synthesis and RTL design.

PHIDEO: High-level synthesis for high throughput applications

1995 ◽  
Vol 9 (1-2) ◽  
pp. 89-104 ◽  
Author(s):  
J. L. Van Meerbergen ◽  
P. E. R. Lippens ◽  
W. F. J. Verhaegh ◽  
A. Van Der Werf
Keyword(s):  
High Throughput ◽  
High Level Synthesis ◽  
High Level

Optimal Design of a VLSI Processor with Spatially and Temporally Parallel Structure

1996 ◽  
Vol 8 (6) ◽  
pp. 516-523
Author(s):  
Michitaka Kameyama ◽  
◽  
Masayuki Sasaki
Keyword(s):  
Delay Time ◽  
Scheduling Algorithm ◽  
High Level Synthesis ◽  
Parallel Structure ◽  
Data Flow Graph ◽  
Silicon Area ◽  
Suitable Combination ◽  
Minimum Delay ◽  
High Level ◽  
Minimum Delay Time

In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to the change of the environment very quickly. Therefore, the development of special-purpose VLSI processors with minimum delay time becomes a very important subject. A suitable combination of spatially parallel and temporally parallel processing is very important to realize the minimum delay time. In this article, we present a scheduling algorithm for high-level synthesis, where the input to the scheduler is a behavioral description viewed as a data flow graph. The scheduler minimizes the delay time under the constraint of a silicon area and I/O pins.

scholarly journals High-Level Synthesis of Multiclass SVM Using Code Refactoring to Classify Brain Cancer from Hyperspectral Images

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1494 ◽  
Author(s):  
Abelardo Baez ◽  
Himar Fabelo ◽  
Samuel Ortega ◽  
Giordana Florimbi ◽  
Emanuele Torti ◽  
...  
Keyword(s):  
Brain Cancer ◽  
Research Field ◽  
Hyperspectral Images ◽  
High Level Synthesis ◽  
Support Vector ◽  
Svm Classifier ◽  
Code Refactoring ◽  
Field Programmable ◽  
And Performance ◽  
High Level

Currently, high-level synthesis (HLS) methods and tools are a highly relevant area in the strategy of several leading companies in the field of system-on-chips (SoCs) and field programmable gate arrays (FPGAs). HLS facilitates the work of system developers, who benefit from integrated and automated design workflows, considerably reducing the design time. Although many advances have been made in this research field, there are still some uncertainties about the quality and performance of the designs generated with the use of HLS methodologies. In this paper, we propose an optimization of the HLS methodology by code refactoring using Xilinx SDSoCTM (Software-Defined System-On-Chip). Several options were analyzed for each alternative through code refactoring of a multiclass support vector machine (SVM) classifier written in C, using two different Zynq®-7000 SoC devices from Xilinx, the ZC7020 (ZedBoard) and the ZC7045 (ZC706). The classifier was evaluated using a brain cancer database of hyperspectral images. The proposed methodology not only reduces the required resources using less than 20% of the FPGA, but also reduces the power consumption −23% compared to the full implementation. The speedup obtained of 2.86× (ZC7045) is the highest found in the literature for SVM hardware implementations.

AN EVOLUTIONARY ALGORITHM FOR THE ALLOCATION PROBLEM IN HIGH-LEVEL SYNTHESIS

2005 ◽  
Vol 14 (02) ◽  
pp. 347-366 ◽  
Author(s):  
HAIDAR M. HARMANANI ◽  
RONY SALIBA
Keyword(s):  
Evolutionary Algorithm ◽  
Allocation Problem ◽  
High Level Synthesis ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Functional Units ◽  
High Level ◽  
The Cost ◽  
Short Time

This paper presents an evolutionary algorithm to solve the datapath allocation problem in high-level synthesis. The method performs allocation of functional units, registers, and multiplexers in addition to controller synthesis with the objective of minimizing the cost of hardware resources. The system handles multicycle functional units as well as structural pipelining. The proposed method was implemented using C++ on a Linux workstation. We tested our method on a set of high-level synthesis benchmarks, all yielding good solutions in a short time. An integration path to Field Programmable Gate Arrays (FPGAs) is provided through VHDL.

scholarly journals Algorithmic-Level Approximate Tensorial SVM Using High-Level Synthesis on FPGA

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 205
Author(s):  
Hamoud Younes ◽  
Ali Ibrahim ◽  
Mostafa Rizk ◽  
Maurizio Valle
Keyword(s):  
Machine Learning ◽  
State Of The Art ◽  
Machine Learning Algorithms ◽  
High Level Synthesis ◽  
Support Vector ◽  
Svm Classifier ◽  
Approximate Computing ◽  
Classification Framework ◽  
Time Latency ◽  
High Level

Approximate Computing Techniques (ACT) are promising solutions towards the achievement of reduced energy, time latency and hardware size for embedded implementations of machine learning algorithms. In this paper, we present the first FPGA implementation of an approximate tensorial Support Vector Machine (SVM) classifier with algorithmic level ACTs using High-Level Synthesis (HLS). A touch modality classification framework was adopted to validate the effectiveness of the proposed implementation. When compared to exact implementation presented in the state-of-the-art, the proposed implementation achieves a reduction in power consumption by up to 49% with a speedup of 3.2×. Moreover, the hardware resources are reduced by 40% while consuming 82% less energy in classifying an input touch with an accuracy loss less than 5%.

scholarly journals On the Difficulty of FSM-based Hardware Obfuscation

2018 ◽  
pp. 293-330 ◽  
Author(s):  
Marc Fyrbiak ◽  
Sebastian Wallat ◽  
Jonathan Déchelotte ◽  
Nils Albartus ◽  
Sinan Böcker ◽  
...  
Keyword(s):  
Reverse Engineering ◽  
Integrated Circuit ◽  
State Of The Art ◽  
Security Analysis ◽  
Third Party ◽  
Level Control ◽  
Finite State ◽  
Field Programmable ◽  
Ip Cores ◽  
High Level

In today’s Integrated Circuit (IC) production chains, a designer’s valuable Intellectual Property (IP) is transparent to diverse stakeholders and thus inevitably prone to piracy. To protect against this threat, numerous defenses based on the obfuscation of a circuit’s control path, i.e. Finite State Machine (FSM), have been proposed and are commonly believed to be secure. However, the security of these sequential obfuscation schemes is doubtful since realistic capabilities of reverse engineering and subsequent manipulation are commonly neglected in the security analysis. The contribution of our work is threefold: First, we demonstrate how high-level control path information can be automatically extracted from third-party, gate-level netlists. To this end, we extend state-of-the-art reverse engineering algorithms to deal with Field Programmable Gate Array (FPGA) gate-level netlists equipped with FSM obfuscation. Second, on the basis of realistic reverse engineering capabilities we carefully review the security of state-of-the-art FSM obfuscation schemes. We reveal several generic strategies that bypass allegedly secure FSM obfuscation schemes and we practically demonstrate our attacks for a several of hardware designs, including cryptographic IP cores. Third, we present the design and implementation of Hardware Nanomites, a novel obfuscation scheme based on partial dynamic reconfiguration that generically mitigates existing algorithmic reverse engineering.

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