Automatic distributed asynchronous control circuit generation from data flow graph for asynchronous high-level synthesis

2002 ◽  
Author(s):  
Euiseok Kim ◽  
Jeong-Gun Lee ◽  
Dong-Ik Lee
Keyword(s):  
Data Flow ◽  
Control Circuit ◽  
High Level Synthesis ◽  
Data Flow Graph ◽  
Flow Graph ◽  
Asynchronous Control ◽  
High Level

scholarly journals System-level Time-stationary Control Synthesis for Pipelined Data Paths

VLSI Design ◽  
1999 ◽  
Vol 9 (2) ◽  
pp. 159-180
Author(s):  
Jong Tae Kim ◽  
Fadi J. Kurdahi ◽  
Noh Byung Park
Keyword(s):  
Data Flow ◽  
System Level ◽  
Control Synthesis ◽  
State Transitions ◽  
Data Flow Graph ◽  
Control Data ◽  
Flow Graph ◽  
High Level ◽  
Horizontal Partitioning ◽  
Stationary Control

We address the prblem of time-stationary control synthesis for pipelined data paths. Control synthesis system accepts scheduled control data flow graph with conditional branches which are produced by high level synthesis tools such as Sehwa [1] as input specification and generates a FSM controller. First a scheduled control/data flow graph is analyzed and the various states are identified. Overlapped states are grouped together to produce L groups where L is the pipeline latency. Next, state transitions are identified and a state table is generated. Finally, a highly optimized FSM controller is implemented by performing horizontal partitioning and the corresponding stae encoding so as to minimize the total controller area. We compared our approach to published work on FSM generation and optimization and the results indicate that our method results in large savings in total controller area.

A High-Throughput Architecture for the SHA-256/224 Compliant With the DSRC Standard

2019 ◽  
Vol 10 (1) ◽  
pp. 98-118
Author(s):  
Imed Saad Ben Dhaou ◽  
Hannu Tenhunen
Keyword(s):  
High Throughput ◽  
Short Range ◽  
State Of The Art ◽  
High Level Synthesis ◽  
Data Flow Graph ◽  
Transformation Techniques ◽  
Safety Message ◽  
Dedicated Short Range Communication ◽  
Field Programmable ◽  
High Level

This article presents a word serial retimed architecture for the SHA-256/224 algorithm. The architecture is compliant with the dedicated-short range communication for safety message authentications. We elaborate three-operand adder architectures suitable for field programmable gate array implementation. Several transformation techniques at the data-flow-graph level have been used to derive the architecture. Synthesis results show that the architecture has high throughput/ slice value compared with state-of-the-art SHA-256 implementations. The article also promulgates a comparison between high-level synthesis and RTL design.

scholarly journals TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis

VLSI Design ◽  
1996 ◽  
Vol 5 (1) ◽  
pp. 77-87 ◽  
Author(s):  
C. P. Ravikumar ◽  
V. Saxena
Keyword(s):  
Genetic Algorithm ◽  
Data Flow ◽  
Middle Level ◽  
Three Dimensions ◽  
Initial Population ◽  
Data Path ◽  
Data Flow Graph ◽  
Flow Graph ◽  
Mutation Operators ◽  
Average Latency

In this paper, we describe TOGAPS, a Testability-Oriented Genetic Algorithm for Pipeline Synthesis. The input to TOGAPS is an unscheduled data flow graph along with a specification of the desired pipeline latency. TOGAPS generates a register-level description of a datapath which is near-optimal in terms of area, meets the latency requirement, and is highly testable. Genetic search is employed to explore a 3-D search space, the three dimensions being the chip area, average latency, and the testability of the datapath. Testability of a design is evaluated by counting the number of self-loops in the structure graph of the data path. Each design is characterized by a four-tuple consisting of (i) the latency and schedule information, (ii) the module allocation, (iii) operation-to-module binding, and (iv) value-to-register binding. Accordingly, we maintain the population of designs in a hierarchical manner. The topmost level of this hierarchy consists of the latency and schedule information, which together characterize the timing performance of the design. The middle level of the hierarchy consists of a number of allocations for a given latency/schedule duplet. The lowest level of the hierarchy consists of a number of bindings for a specific latency/schedule/ allocation. An initial population of designs is constructed from the given data flow graph using different latency cycles whose average latency is in the specified range. Multiple scheduling heuristics are used to generate schedules for the DFG. For each of the resulting scheduled data flow graphs, we decide on an allocation of modules and registers based on a lower bound estimated using the schedule and latency information. The operation-to-module binding and the value-to-register binding are then carried out. A fitness measure is evaluated for each of the resulting data paths; this fitness measure includes one component for each of the three search dimensions. Crossover and mutation operators are used to generate new designs from the current set of parent designs. The crossover operator attempts to combine the properties of two designs. The mutation operators include addition and deletion of pure delays before scheduling, as well as changes in the register and module allocation prior to binding. The genetic algorithm applies the rule of the survival of the fittest to obtain nearoptimal solution to the otherwise intractable problem of data path synthesis. We have implemented TOGAPS on a Sun/SPARC 10 and studied its performance on a number of benchmark examples. Results indicate that TOGAPS finds area-optimal datapaths for the specified latency cycle, while reducing the number of self-loops in the data path.

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