Analysis of the thickness-dependent electrical characteristics in pentacene field-effect devices

2014 ◽  
Vol 65 (1) ◽  
pp. 87-91
Author(s):  
Dongwook Kim ◽  
Hyunji Shin ◽  
Jong Sun Choi ◽  
Xue Zhang ◽  
Ji-Ho Park ◽  
...  
Keyword(s):  
Field Effect ◽  
Electrical Characteristics ◽  
Field Effect Devices

Effects of gate electrode work function on electrical characteristics of pentacene-based field-effect devices

2010 ◽  
Vol 97 (9) ◽  
pp. 093301 ◽  
Author(s):  
Jaehoon Park ◽  
Hey Min Kim ◽  
Dong Wook Kim ◽  
Jong Sun Choi
Keyword(s):  
Work Function ◽  
Field Effect ◽  
Electrical Characteristics ◽  
Gate Electrode ◽  
Field Effect Devices

scholarly journals Gallium Arsenide as a Competitor to Silicon for High-speed Amplification and Switching

1982 ◽  
Vol 35 (6) ◽  
pp. 749
Author(s):  
PH Ladbrooke ◽  
DR Debuf ◽  
K Nanayakkara ◽  
DR Wilkins
Keyword(s):  
Field Effect ◽  
High Speed ◽  
Field Effect Transistors ◽  
Electrical Characteristics ◽  
Electrical Behaviour ◽  
Technological Factors ◽  
Ballistic Electron ◽  
Ballistic Electron Transport ◽  
Field Effect Devices ◽  
Transport Effects

A review is given of the physical and technological factors which affect the electrical behaviour of field-effect devices for high-speed applications. Ballistic electron transport is shown to lead to an electron transit time under the gate electrode which is shorter in GaAs than in Si field-effect transistors (FETs), providing a possible basis for exploitation of transport effects in high-speed devices. Some electrical characteristics of practical Si and GaAs field-effect structures are presented.

Effect of Surrounded-Channel Structure on Electrical Characteristics of $c$ -Axis Aligned Crystalline In–Ga–Zn–O Field-Effect Transistor

2015 ◽  
Vol 36 (4) ◽  
pp. 309-311 ◽  
Author(s):  
Yoshiyuki Kobayashi ◽  
Daisuke Matsubayashi ◽  
Suguru Hondo ◽  
Tsutomu Yamamoto ◽  
Yutaka Okazaki ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Channel Structure ◽  
Electrical Characteristics ◽  
Effect Transistor

scholarly journals Label-free Electrostatic Detection of DNA Amplification by PCR Using Capacitive Field-effect Devices

2016 ◽  
Vol 168 ◽  
pp. 514-517 ◽  
Author(s):  
A. Poghossian ◽  
T.S. Bronder ◽  
S. Scheja ◽  
C. Wu ◽  
T. Weinand ◽  
...  
Keyword(s):  
Field Effect ◽  
Dna Amplification ◽  
Label Free ◽  
Field Effect Devices

Mos digital‐to‐analog converter employing scaled field effect devices

1981 ◽  
Vol 69 (3) ◽  
pp. 889-889
Author(s):  
Ajay K. Puri ◽  
Michael J. Caruso ◽  
Stanley M. Dennison ◽  
Jay Brown
Keyword(s):  
Field Effect ◽  
Digital To Analog Converter ◽  
Analog Converter ◽  
Field Effect Devices ◽  
Digital To Analog

SILICON ON RAISED INSULATOR FIELD EFFECT DIODE (SORI-FED) FOR ALLEVIATING SCALING PROBLEM IN FED

2014 ◽  
Vol 28 (05) ◽  
pp. 1450038 ◽  
Author(s):  
MAHDI VADIZADEH ◽  
MORTEZA FATHIPOUR ◽  
GHAFAR DARVISH
Keyword(s):  
Delay Time ◽  
Field Effect ◽  
Channel Length ◽  
Gate Delay ◽  
Electrical Characteristics ◽  
Band To Band Tunneling ◽  
Main Components ◽  
Channel Lengths ◽  
Length Scaling ◽  
The Impact

One of the main shortcomings in a field effect diode (FED) is its scaling. Use of an oxide layer in the channel is proposed to enhance the control of the gate on the channel carriers. This is the so-called silicon on raised insulator FED (SORI-FFD) structure. The Shockley–Read–Hall (SRH) mechanism is one of the main components of leakage current in FED devices. The potential induced by the gates in the OFF-state of a SORI-FFD, is larger than that induced by the gates of a regular FED. This reduces, SRH recombination rate. Hence, OFF-state characteristics of the SORI-FED device improves. We evaluate the impact of band-to-band tunneling (BTBT) on the electrical characteristics of Modified FED (M-FED).We show that for channel lengths of 35 nm and lower this device does not turn off. While, the proposed structure makes device channel length scaling possible down to 15 nm. We will also compare electrical characteristics of SORI-FED and M-FED using three metrics: gate delay time versus channel length, gate delay time versus I ON /I OFF ratio and energy-delay product versus channel length. Benchmarking results show the proposed FED structure provides improvement in I ON /I OFF ratio and holds promise for future logic transistor applications.

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