scholarly journals Low-Latency QC-LDPC Encoder Design for 5G NR

Sensors ◽  
2021 ◽  
Vol 21 (18) ◽  
pp. 6266
Author(s):  
Yunke Tian ◽  
Yong Bai ◽  
Dake Liu
Keyword(s):  
Cmos Technology ◽  
Base Station ◽  
Parallel Structure ◽  
Low Latency ◽  
Time Interval ◽  
Parity Check ◽  
Code Length ◽  
New Radio ◽  
System Frequency ◽  
Transmission Time Interval

In order to meet the low latency and high throughput requirements of data transmission in 5th generation (5G) New Radio (NR), it is necessary to minimize the low power encoding hardware latency on transmitter and achieve lower base station power consumption within a fixed transmission time interval (TTI). This paper investigates parallel design and implementation of 5G quasi-cyclic low-density parity-check (QC-LDPC) codes encoder. The designed QC-LDPC encoder employs a multi-channel parallel structure to obtain multiple parity check bits and thus reduce encoding latency significantly. The proposed encoder maps high parallelism encoding algorithms to a configurable circuit architecture, achieving flexibility and support for all 5G NR code length and code rate. The experimental results show that under the 800 MHz system frequency, the achieved data throughput ranges from 62 to 257.9 Gbps, and the maximum code length encoding time under base graph 1 (BG1) is only 33.75 ns, which is the critical encoding time of our proposed encoder. Finally, our proposed encoder was synthesized on SMIC 28 nm CMOS technology; the result confirmed the effectiveness and feasibility of our design.

scholarly journals Efficient QC-LDPC Encoder for 5G New Radio

Electronics ◽  
2019 ◽  
Vol 8 (6) ◽  
pp. 668 ◽  
Author(s):  
Tram Thi Bao Nguyen ◽  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Substantial Reduction ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Complexity ◽  
Cmos Technology ◽  
Memory Storage ◽  
Oxide Semiconductor ◽  
Parity Check ◽  
Hardware Complexity ◽  
New Radio ◽  
Encoding Method

This paper presents a novel efficient encoding method and a high-throughput low-complexity encoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes for the 5th-generation (5G) New Radio (NR) standard. By storing the quantized value of the permutation information for each submatrix instead of the whole parity check matrix, the required memory storage size is considerably reduced. In addition, sharing techniques are employed to reduce the hardware complexity. The encoding complexity of the proposed method was analyzed, and indicated a substantial reduction in the required area as well as memory storage when compared with existing state-of-the-art encoding approaches. The proposed method requires only 61% gate area, and 11% ROM storage when compared with a similar LDPC encoder using the Richardson–Urbanke method. Synthesis results on TSMC 65-nm complementary metal-oxide semiconductor (CMOS) technology with different submatrix sizes were carried out, which confirmed that the design methodology is flexible and can be adapted for multiple submatrix sizes. For all the considered submatrix sizes, the throughput ranged from 22.1–202.4 Gbps, which sufficiently meets the throughput requirement for the 5G NR standard.

scholarly journals Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1106
Author(s):  
Vladimir L. Petrović ◽  
Dragomir M. El Mezeni ◽  
Andreja Radošević
Keyword(s):  
Channel Coding ◽  
Parallel Architecture ◽  
Ldpc Codes ◽  
Parity Check ◽  
Case Scenario ◽  
New Radio ◽  
Physical Channel ◽  
Computationally Intensive ◽  
Hardware Processing ◽  
Usage Efficiency

Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE.

scholarly journals High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 700
Author(s):  
Yufei Zhu ◽  
Zuocheng Xing ◽  
Zerun Li ◽  
Yang Zhang ◽  
Yifan Hu
Keyword(s):  
High Performance ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Cmos Technology ◽  
Area Efficiency ◽  
Prior Art ◽  
New Radio ◽  
High Area ◽  
Significant Area ◽  
Area Efficient

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

scholarly journals An overview of channel coding for 5G NR cellular communications

2019 ◽  
Vol 8 ◽  
Author(s):  
Jung Hyun Bae ◽  
Ahmed Abotabl ◽  
Hsien-Ping Lin ◽  
Kee-Bong Song ◽  
Jungwon Lee
Keyword(s):  
Channel Coding ◽  
Ldpc Codes ◽  
Low Latency ◽  
Polar Codes ◽  
Coding Scheme ◽  
Coding Schemes ◽  
Successive Cancellation ◽  
New Radio ◽  
Key Characteristics ◽  
User Data

AbstractA 5G new radio cellular system is characterized by three main usage scenarios of enhanced mobile broadband (eMBB), ultra-reliable and low latency communications (URLLC), and massive machine type communications, which require improved throughput, latency, and reliability compared with a 4G system. This overview paper discusses key characteristics of 5G channel coding schemes which are mainly designed for the eMBB scenario as well as for partial support of the URLLC scenario focusing on low latency. Two capacity-achieving channel coding schemes of low-density parity-check (LDPC) codes and polar codes have been adopted for 5G where the former is for user data and the latter is for control information. As a coding scheme for data, 5G LDPC codes are designed to support high throughput, a variable code rate and length and hybrid automatic repeat request in addition to good error correcting capability. 5G polar codes, as a coding scheme for control, are designed to perform well with short block length while addressing a latency issue of successive cancellation decoding.

scholarly journals Design of Short, High-Rate DVB-S2-Like Semi-Regular LDPC Codes

2008 ◽  
Vol 2008 ◽  
pp. 1-4
Author(s):  
Luca Barletta ◽  
Arnaldo Spalvieri
Keyword(s):  
Coded Modulation ◽  
High Rate ◽  
Parity Check ◽  
Code Length ◽  
Carrier Recovery ◽  
Low Density Parity Check ◽  
Novel Approach ◽  
Parity Check Codes ◽  
Moderate Length

This work focuses on high-rate () moderate-length () low-density parity-check codes. High-rate codes allow to maintain good quality of the preliminary decisions that are used in carrier recovery, while a moderate code length allows to keep the latency low. The interleaver of the LDPC matrix that we consider is inspired to the DVB-S2 standard one. A novel approach for avoiding short cycles is analyzed. A modified BP decoding algorithm is applied in order to deal with longer cycles. Simulations and results for the AWGN channel are presented, both for BPSK signalling and for coded modulation based on the partition .

scholarly journals Orthros: A Low-Latency PRF

2021 ◽  
pp. 37-77
Author(s):  
Subhadeep Banik ◽  
Takanori Isobe ◽  
Fukang Liu ◽  
Kazuhiko Minematsu ◽  
Kosei Sakamoto
Keyword(s):  
Hardware Implementation ◽  
Block Cipher ◽  
State Of The Art ◽  
Security Analysis ◽  
Parallel Structure ◽  
Low Latency ◽  
Round Function ◽  
Minimum Latency ◽  
Primary Focus ◽  
Pseudorandom Function

We present Orthros, a 128-bit block pseudorandom function. It is designed with primary focus on latency of fully unrolled circuits. For this purpose, we adopt a parallel structure comprising two keyed permutations. The round function of each permutation is similar to Midori, a low-energy block cipher, however we thoroughly revise it to reduce latency, and introduce different rounds to significantly improve cryptographic strength in a small number of rounds. We provide a comprehensive, dedicated security analysis. For hardware implementation, Orthros achieves the lowest latency among the state-of-the-art low-latency primitives. For example, using the STM 90nm library, Orthros achieves a minimum latency of around 2.4 ns, while other constructions like PRINCE, Midori-128 and QARMA9-128- σ0 achieve 2.56 ns, 4.10 ns, 4.38 ns respectively.

scholarly journals SoftPSN: Software-Defined Resource Slicing for Low-Latency Reliable Public Safety Networks

2018 ◽  
Vol 2018 ◽  
pp. 1-7 ◽  
Author(s):  
Anteneh A. Gebremariam ◽  
Muhammad Usman ◽  
Riccardo Bassoli ◽  
Fabrizio Granelli
Keyword(s):  
Public Safety ◽  
First Responders ◽  
Base Station ◽  
Low Latency ◽  
Radio Resource ◽  
Life Saving ◽  
Before And After ◽  
Simulation Results ◽  
Emergency Scenarios ◽  
Safety Applications

Achieving the low-latency constraints of public safety applications during disaster could be life-saving. In the context of public safety scenarios, in this paper, we propose an efficient radio resource slicing algorithm that enables first responders to deliver their life-saving activities effectively. We used the tool of stochastic geometry to model the base station distribution before and after a disaster. In addition, under this umbrella, we also proposed an example of public safety scenario, ultrareliable low-latency file sharing, via in-band device-to-device (D2D) communication. The example scenario is implemented in NS-3. The simulation results show that radio resource slicing and prioritization of first responders resources can ensure ultrareliable low-latency communication (URLLC) in emergency scenarios.

A Low-Power High-Linear Time-to-Digital Converter for Measuring R-R Intervals in ECG Signal Optimized by Neural Network and TLBO Algorithm

2018 ◽  
Vol 28 (02) ◽  
pp. 1950021
Author(s):  
B. Ghanavati ◽  
E. Abiri ◽  
M. R. Salehi ◽  
N. Azhdari
Keyword(s):  
Neural Network ◽  
Dynamic Range ◽  
Linear Time ◽  
Optimization Method ◽  
Cmos Technology ◽  
Time Interval ◽  
Digital Converter ◽  
Two Stage ◽  
Time To Digital Converter ◽  
Tlbo Algorithm

In this paper, a two-stage time interpolation time-to-digital converter (TDC) is proposed to achieve adequate resolution and wide dynamic range for measuring R-R intervals in QRS detection. The architecture is based on a coarse counter and a couple of two-stage interpolator circuit in order to improve the conversion linearity. The proposed TDC is modeled with the neural network, while the teacher–learner-based optimization algorithm (TLBO) is used to optimize the integral nonlinearity (INL) of the proposed TDC. The proposed optimization method shows a characteristic close to the ideal output of the TDC behavior over a wide input range. Using the achieved results of the TLBO algorithm simulation results using CADENCE VIRTUOSO and standard 180[Formula: see text]nm CMOS technology shows 1.2[Formula: see text]s dynamic range, 100[Formula: see text]ns resolution, 0.19[Formula: see text]mW power consumption and area of 0.16[Formula: see text]mm2. The proposed circuit can find application in biomedical engineering systems and other fields where long and accurate time interval measurement is needed.

scholarly journals AgriTrust—A Trust Management Approach for Smart Agriculture in Cloud-based Internet of Agriculture Things

Sensors ◽  
2020 ◽  
Vol 20 (21) ◽  
pp. 6174 ◽  
Author(s):  
Kamran Ahmad Awan ◽  
Ikram Ud Din ◽  
Ahmad Almogren ◽  
Hisham Almajed
Keyword(s):  
Trust Management ◽  
Service Providers ◽  
Base Station ◽  
Security And Privacy ◽  
Management Approach ◽  
Time Interval ◽  
Management Mechanism ◽  
Trust Degree ◽  
Smart Agriculture ◽  
Compromised Nodes

Internet of Things (IoT) provides a diverse platform to automate things where smart agriculture is one of the most promising concepts in the field of Internet of Agriculture Things (IoAT). Due to the requirements of more processing power for computations and predictions, the concept of Cloud-based smart agriculture is proposed for autonomic systems. This is where digital innovation and technology helps to improve the quality of life in the area of urbanization expansion. For the integration of cloud in smart agriculture, the system is shown to have security and privacy challenges, and most significantly, the identification of malicious and compromised nodes along with a secure transmission of information between sensors, cloud, and base station (BS). The identification of malicious and compromised node among soil sensors communicating with the BS is a notable challenge in the BS to cloud communications. The trust management mechanism is proposed as one of the solutions providing a lightweight approach to identify these nodes. In this article, we have proposed a novel trust management mechanism to identify malicious and compromised nodes by utilizing trust parameters. The trust mechanism is an event-driven process that computes trust based on the pre-defined time interval and utilizes the previous trust degree to develop an absolute trust degree. The system also maintains the trust degree of a BS and cloud service providers using distinct approaches. We have also performed extensive simulations to evaluate the performance of the proposed mechanism against several potential attacks. In addition, this research helps to create friendlier environments and efficient agricultural productions for the migration of people to the cities.

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