scholarly journals Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 137 ◽  
Author(s):  
Bo Gao ◽  
Xin Li ◽  
Jie Sun ◽  
Jianhui Wu
Keyword(s):  
High Resolution ◽  
Low Noise ◽  
Sar Adc ◽  
Total Power ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Signal To Noise ◽  
Analog To Digital ◽  
High Bandwidth

The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal-to-noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub-ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator’s resolution in both stages for a given power budget, compared with a conventional Pipelined-SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post-layout simulation results show that the proposed hybrid ADC achieves a signal-to-noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW.

scholarly journals A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm

Symmetry ◽  
2020 ◽  
Vol 12 (1) ◽  
pp. 165
Author(s):  
Shouping Li ◽  
Yang Guo ◽  
Jianjun Chen ◽  
Bin Liang
Keyword(s):  
Successive Approximation ◽  
High Speed ◽  
Low Noise ◽  
Digital Calibration ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Calibration Algorithm

This paper presents a foreground digital calibration algorithm based on a dynamic comparator that aims to reduce comparator offset and capacitor mismatch, as well as improve the performance of the successive approximation analog-to-digital converter (SARADC). The dynamic comparator is designed with two preamplifiers and one latch to facilitate high speed, high precision, and low noise. The foreground digital calibration algorithm provides high speed with minimal area consumption. This design is implemented on a 12-bit 30 MS/s SARADC with a standard 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) process. The simulation Nyquist 68.56 dB signal-to-noise-and-distortion ratio (SNDR) and 84.45 dBc spurious free dynamic range (SFDR) at 30 MS/s, differential nonlinearity (DNL) and integral nonlinearity (INL) are within 0.64 Least Significant Bits (LSB) and 1.3 LSB, respectively. The ADC achieves an effective number of bits (ENOB) of 11.08 and a figure-of-merit (FoM) of 39.45 fJ/conv.-step.

100 MS/s, 10-BIT ADC USING PIPELINED SUCCESSIVE APPROXIMATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450057
Author(s):  
SAHAR SARAFI ◽  
KHEYROLLAH HADIDI ◽  
EBRAHIM ABBASPOUR ◽  
ABU KHARI BIN AAIN ◽  
JAVAD ABBASZADEH
Keyword(s):  
Successive Approximation ◽  
Sar Adc ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Process Technology ◽  
Total Conversion ◽  
Analog To Digital ◽  
Simulation Results

This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply.

Design of Low Power and High Precision Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) Based on Piecewise Capacitance and Calibration Technique

2020 ◽  
Vol 15 (4) ◽  
pp. 478-486
Author(s):  
Sheng-Biao An ◽  
Li-Xin Zhao ◽  
Shi-Cong Yang ◽  
Tao An ◽  
Rui-Xia Yang
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Dynamic Range ◽  
Sar Adc ◽  
Total Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Total Power Consumption

This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%. The test chip fabricated in 180 nm Complementary Metal Oxide Semiconductor (CMOS) occupied an active area of 0.12 mm 2 . At 10 MS/s, a signal-to-noise and distortion ratio (SNDR) of 57.70 dB and a spurious-free dynamic range (SFDR) of 55.63 dB are measured with 1.68 Vpp differential-mode input signal. The total power consumption is 690 μW corresponding to 67 fJ/conversion step figure of merit.

A High-Resolution and Low Offset Delta-Sigma Analog to Digital Converter for Detecting Photoplethysmography Signal

2021 ◽  
Author(s):  
Eka Fitrah Pribadi ◽  
Rajeev Kumar Pandey ◽  
Paul C.-P. Chao
Keyword(s):  
High Resolution ◽  
Continuous Time ◽  
Operational Amplifier ◽  
High Frequency ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Low Offset

Abstract A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1–10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the high-frequency region. The DS ADC circuitry consists of a second-order continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746μm × 399 μm and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61μW. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.

High Temperature Analog-to-Digital Converter Reliability Testing

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000245-000252 ◽  
Author(s):  
Bruce W. Ohme ◽  
Mark R. Larson
Keyword(s):  
High Temperature ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Reliability Testing ◽  
Test Results ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Life Test ◽  
Analog To Digital ◽  
Post Stress

Initial test results have been previously reported for a high-temperature (225°C) 12-bit analog-to-digital converter (HTADC12) fabricated using a production high-temperature silicon-on-insulator (SOI) CMOS process and assembled in hermetically sealed ceramic packages (ref. 1). Reliability test results for the HTADC12 are presented including parametric and functional test results from 1500 hours of dynamic life test at 250°C as well 1000 temperature cycles from −65°C to 200°C. Results of post-stress wirebond, and die bond testing are also provided.

scholarly journals ANALYSIS AND DESIGN OF A NEW STRUCTURE FOR 10-BIT 350MS/S PIPELINE ANALOG TO DIGITAL CONVERTER

2019 ◽  
Vol 8 (3) ◽  
Author(s):  
Arash Rezapour ◽  
Mohammad Bagher Tavakoli ◽  
Farbod Setoudeh
Keyword(s):  
Power Supply ◽  
Data Transfer ◽  
Open Loop ◽  
Total Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Analysis And Design ◽  
Second Stage ◽  
Total Power Consumption

A 10-bit pipelined Analog to Digital converter is proposed in this paper with using 0.18 µm TSMC technology. In this paper, a new structure is proposed to increase the speed of the pipeline analog to digital convertor. So at the first stage is not used the amplifier and instead the buffer is used for data transfer to the second stage. The speed of this converter is 350MS/s. An amplifier circuit with accurate gain of 6 and a very accurate unit gain buffer circuit that are open loop with a new structure were. used. In this Converter, the first 3 bits are extracted simultaneously with sampling. The proposed analog-to-digital converter was designed with the total power consumption 75mW using power supply of 1.8v.

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