scholarly journals HARP: Hierarchical Attention Oriented Region-Based Processing for High-Performance Computation in Vision Sensor

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1757
Author(s):  
Pankaj Bhowmik ◽  
Md Jubaer Hossain Pantho ◽  
Christophe Bobda
Keyword(s):  
Integrated Circuit ◽  
Focal Plane ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Autonomous Driving ◽  
Image Sensor ◽  
Oxide Semiconductor ◽  
Smart Cameras ◽  
Hierarchical Processing ◽  
Large Bandwidth

Cameras are widely adopted for high image quality with the rapid advancement of complementary metal-oxide-semiconductor (CMOS) image sensors while offloading vision applications’ computation to the cloud. It raises concern for time-critical applications such as autonomous driving, surveillance, and defense systems since moving pixels from the sensor’s focal plane are expensive. This paper presents a hardware architecture for smart cameras that understands the salient regions from an image frame and then performs high-level inference computation for sensor-level information creation instead of transporting raw pixels. A visual attention-oriented computational strategy helps to filter a significant amount of redundant spatiotemporal data collected at the focal plane. A computationally expensive learning model is then applied to the interesting regions of the image. The hierarchical processing in the pixels’ data path demonstrates a bottom-up architecture with massive parallelism and gives high throughput by exploiting the large bandwidth available at the image source. We prototype the model in field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) for integrating with a pixel-parallel image sensor. The experiment results show that our approach achieves significant speedup while in certain conditions exhibits up to 45% more energy efficiency with the attention-oriented processing. Although there is an area overhead for inheriting attention-oriented processing, the achieved performance based on energy consumption, latency, and memory utilization overcomes that limitation.

scholarly journals Angular Light, Polarization and Stokes Parameters Information in a Hybrid Image Sensor with Division of Focal Plane

Sensors ◽  
2020 ◽  
Vol 20 (12) ◽  
pp. 3391
Author(s):  
Francelino Freitas Carvalho ◽  
Carlos Augusto de Moraes Cruz ◽  
Greicy Costa Marques ◽  
Kayque Martins Cruz Damasceno
Keyword(s):  
Integrated Circuit ◽  
Incident Angle ◽  
Complementary Metal Oxide Semiconductor ◽  
Image Sensor ◽  
Light Polarization ◽  
Oxide Semiconductor ◽  
Stokes Parameters ◽  
New Paradigm ◽  
Depth Sensing ◽  
3D Image Reconstruction

Targeting 3D image reconstruction and depth sensing, a desirable feature for complementary metal oxide semiconductor (CMOS) image sensors is the ability to detect local light incident angle and the light polarization. In the last years, advances in the CMOS technologies have enabled dedicated circuits to determine these parameters in an image sensor. However, due to the great number of pixels required in a cluster to enable such functionality, implementing such features in regular CMOS imagers is still not viable. The current state-of-the-art solutions require eight pixels in a cluster to detect local light intensity, incident angle and polarization. The technique to detect local incident angle is widely exploited in the literature, and the authors have shown in previous works that it is possible to perform the job with a cluster of only four pixels. In this work, the authors explore three novelties: a mean to determine three of four Stokes parameters, the new paradigm in polarization cluster-pixel design, and the extended ability to detect both the local light angle and intensity. The features of the proposed pixel cluster are demonstrated through simulation program with integrated circuit emphasis (SPICE) of the regular Quadrature Pixel Cluster and Polarization Pixel Cluster models, the results of which are compliant with experimental results presented in the literature.

scholarly journals Materials and processing approaches for foundry-compatible transient electronics

2017 ◽  
Vol 114 (28) ◽  
pp. E5522-E5529 ◽  
Author(s):  
Jan-Kai Chang ◽  
Hui Fang ◽  
Christopher A. Bower ◽  
Enming Song ◽  
Xinge Yu ◽  
...  
Keyword(s):  
Data Storage ◽  
Integrated Circuit ◽  
High Performance ◽  
Electronic Materials ◽  
Electronic Devices ◽  
Complementary Metal Oxide Semiconductor ◽  
Water Soluble ◽  
Oxide Semiconductor ◽  
Cost Structures ◽  
Functional Capabilities

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for “green” electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are (i) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, (ii) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and (iii) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries.

scholarly journals Low-Cost Microbolometer Type Infrared Detectors

Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 800
Author(s):  
Le Yu ◽  
Yaozu Guo ◽  
Haoyu Zhu ◽  
Mingcheng Luo ◽  
Ping Han ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Focal Plane ◽  
Technological Development ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Micro Electro Mechanical System ◽  
Focal Plane Arrays ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Cmos Compatible

The complementary metal oxide semiconductor (CMOS) microbolometer technology provides a low-cost approach for the long-wave infrared (LWIR) imaging applications. The fabrication of the CMOS-compatible microbolometer infrared focal plane arrays (IRFPAs) is based on the combination of the standard CMOS process and simple post-CMOS micro-electro-mechanical system (MEMS) process. With the technological development, the performance of the commercialized CMOS-compatible microbolometers shows only a small gap with that of the mainstream ones. This paper reviews the basics and recent advances of the CMOS-compatible microbolometer IRFPAs in the aspects of the pixel structure, the read-out integrated circuit (ROIC), the focal plane array, and the vacuum packaging.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Characterization of High-Performance Polycrystalline Silicon Complementary Metal–Oxide–Semiconductor Circuits

2007 ◽  
Vol 46 (1) ◽  
pp. 51-55 ◽  
Author(s):  
Genshiro Kawachi ◽  
Yoshiaki Nakazaki ◽  
Hiroyuki Ogawa ◽  
Masayuki Jyumonji ◽  
Noritaka Akita ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Polycrystalline Silicon ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Circuits

scholarly journals A Multiplexed Chemical Sensing CMOS Imager

2021 ◽  
Author(s):  
Di Wang ◽  
Fenni Zhang ◽  
Kyle Mallires ◽  
Vishal Tipparaju ◽  
Jingjing Yu ◽  
...  
Keyword(s):  
Chemical Sensing ◽  
High Performance ◽  
Health Management ◽  
Complementary Metal Oxide Semiconductor ◽  
Spot Size ◽  
Oxide Semiconductor ◽  
Colorimetric Sensing ◽  
Widespread Application ◽  
Cmos Imager ◽  
Cmos Chip

Abstract A miniaturized and multiplexed chemical sensing technology is urgently needed to empower mobile devices, Internet-of-Things (IoTs) and robots for various new applications. Here, we show that a complementary metal-oxide-semiconductor (CMOS) imager can be turned into a multiplexed colorimetric sensing chip by coating micron-scale colorimetric sensing spots on the imager surface. Each sensing spot contains chemical sensing materials and nanoparticles for colorimetric signal enhancement. The sensitivity is spot-size invariant, and high-performance chemical sensing can be achieved on sensing spot as small as ~ 10 µm. This great scalability combined with millions of pixels of a CMOS imager offers a promising platform for highly integrated chemical sensors. Moreover, the chemical CMOS chip can be readily integrated with mobile electronics. As a proof-of-concept, we have built a smartphone accessary based on this chemical CMOS chip for personal health management. We anticipate that this new platform will pave the way for the widespread application of chemical sensing, such as mobile health (mHealth), IoTs, electronic nose, and smart homes.

scholarly journals Effects of Process Variations in a HCMOS IC using a Monte Carlo SPICE Simulation

2017 ◽  
pp. 11-16
Author(s):  
Widianto Widianto ◽  
Lailis Syafaah ◽  
Nurhadi Nurhadi
Keyword(s):  
Monte Carlo ◽  
Integrated Circuit ◽  
High Speed ◽  
Evaluation Method ◽  
Complementary Metal Oxide Semiconductor ◽  
Process Variations ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Spice Simulation ◽  
Simulation Results

In this paper, effects of process variations in a HCMOS (High-Speed Complementary Metal Oxide Semiconductor) IC (Integrated Circuit) are examined using a Monte Carlo SPICE (Simulation Program with Integrated Circuit Emphasis) simulation. The variations of the IC are L and VTO variations. An evaluation method is used to evaluate the effects of the variations by modeling it using a normal (Gaussian) distribution. The simulation results show that the IC may be detected as a defective IC caused by the variations based on large supply currents flow to it. 

The Effect of Strain on the Formation of Dislocations at the SiGe/Si Interface

MRS Bulletin ◽  
1996 ◽  
Vol 21 (4) ◽  
pp. 38-44 ◽  
Author(s):  
F.K. LeGoues
Keyword(s):  
Metal Oxide ◽  
High Speed ◽  
High Performance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Design Rule ◽  
Strained Si

Recently much interest has been devoted to Si-based heteroepitaxy, and in particular, to the SiGe/Si system. This is mostly for economical reasons: Si-based technology is much more advanced, is widely available, and is cheaper than GaAs-based technology. SiGe opens the door to the exciting (and lucrative) area of Si-based high-performance devices, although optical applications are still limited to GaAs-based technology. Strained SiGe layers form the base of heterojunction bipolar transistors (HBTs), which are currently used in commercial high-speed analogue applications. They promise to be low-cost compared to their GaAs counterparts and give comparable performance in the 2-20-GHz regime. More recently we have started to investigate the use of relaxed SiGe layers, which opens the door to a wider range of application and to the use of SiGe in complementary metal oxide semiconductor (CMOS) devices, which comprise strained Si and SiGe layers. Some recent successes include record-breaking low-temperature electron mobility in modulation-doped layers where the mobility was found to be up to 50 times better than standard Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Even more recently, SiGe-basedp-type MOSFETS were built with oscillation frequency of up to 50 GHz, which is a new record, in anyp-type material for the same design rule.

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